EP 1196951 B1 20130403 - TSOP MEMORY CHIP HOUSING ARRANGEMENT
Title (en)
TSOP MEMORY CHIP HOUSING ARRANGEMENT
Title (de)
TSOP-SPEICHERCHIPGEHÄUSEANORDNUNG
Title (fr)
ENSEMBLE DE BOITIERS A PUCE MEMOIRE DU TYPE BOITIER MINCE A CONNECTIONS COURTES (TSOP)
Publication
Application
Priority
- DE 0002292 W 20000713
- DE 19933265 A 19990715
Abstract (en)
[origin: DE19933265A1] The invention relates to an arrangement of at least two stacked TSOP memory chip housings, each comprising at least one memory chip with several pins arranged inside the TSOP memory chip housing, whereby said pins are guided through the respective TSOP memory chip housing and connected, via a wiring arrangement, to pins which are guided through a directly adjacent TSOP memory chip housing. In order to create a housing stack using an automated assembly process which is as inexpensive as possible and to enable said stack to be produced in the easiest possible manner, the wiring arrangement is provided in the form of leadfames which are respectively arranged between or arranged laterally between the individual TSOP memory chip housings.
IPC 8 full level
G11C 5/06 (2006.01); G11C 5/12 (2006.01); H01L 25/10 (2006.01); H01L 25/11 (2006.01); H01L 25/18 (2006.01); H01R 9/03 (2006.01); H01R 11/01 (2006.01)
CPC (source: EP US)
G11C 5/06 (2013.01 - EP US); G11C 5/12 (2013.01 - EP US); H01L 25/105 (2013.01 - EP US); H01L 2225/1029 (2013.01 - EP US); H01L 2225/107 (2013.01 - EP US); H01L 2924/0002 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
DE 19933265 A1 20010201; EP 1196951 A1 20020417; EP 1196951 B1 20130403; JP 2003505861 A 20030212; JP 3691016 B2 20050831; US 2003012002 A1 20030116; US 2003127723 A1 20030710; US 6538895 B2 20030325; WO 0106562 A1 20010125
DOCDB simple family (application)
DE 19933265 A 19990715; DE 0002292 W 20000713; EP 00954331 A 20000713; JP 2001510916 A 20000713; US 37576203 A 20030226; US 4781502 A 20020115