Global Patent Index - EP 1212626 A4

EP 1212626 A4 20060524 - METHOD FOR TESTING CIRCUITS

Title (en)

METHOD FOR TESTING CIRCUITS

Title (de)

Verfahren zum Prüfen von Schattungen

Title (fr)

PROCEDE DESTINE A TESTER DES CIRCUITS

Publication

EP 1212626 A4 20060524 (EN)

Application

EP 00939316 A 20000519

Priority

  • US 0013862 W 20000519
  • US 13480099 P 19990519

Abstract (en)

[origin: WO0070358A1] The present disclosure relates to a method for testing a circuit having analog components. The method comprises performing a low-cost optimized test on the circuit by applying an optimized input stimulus (20) to the circuit, capturing the circuit response (22) to the input stimulus (20) applied to the circuit, evaluating the circuit response to predict whether the performance parameters of the circuit satisfies predetermined specifications (24) for the circuit, and making a pass/fail determination (26) for the circuit based upon the evaluating of the circuit response.

IPC 1-7

G01R 31/02

IPC 8 full level

G01R 31/01 (2020.01); G01R 31/28 (2006.01); G01R 31/3163 (2006.01)

CPC (source: EP US)

G01R 31/01 (2013.01 - EP US); G01R 31/2846 (2013.01 - EP); G01R 31/3163 (2013.01 - EP)

Citation (search report)

  • [X] US 4647846 A 19870303 - MALKIN DOV B [US]
  • [X] US 4168527 A 19790918 - WINKLER DEAN A
  • [X] US 4044244 A 19770823 - FOREMAN STEVEN H, et al
  • [X] US 5819208 A 19981006 - CARTER MALCOLM EDWARD [GB]
  • [X] US 5327437 A 19940705 - BALZER RAYMOND J [US]
  • [A] WO 9855880 A1 19981210 - OPMAXX INC [US], et al
  • [X] VARIYAM P N ET AL: "Specification-Driven Test Design for Analog Circuits", DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, 1998. PROCEEDINGS., 1998 IEEE INTERNATIONAL SYMPOSIUM ON AUSTIN, TX, USA 2-4 NOV. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 2 November 1998 (1998-11-02), pages 335 - 340, XP010315434, ISBN: 0-8186-8832-7
  • [X] VARIYAM P N ET AL: "Enhancing test effectiveness for analog circuits using synthesized measurements", VLSI TEST SYMPOSIUM, 1998. PROCEEDINGS. 16TH IEEE MONTEREY, CA, USA 26-30 APRIL 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 26 April 1998 (1998-04-26), pages 132 - 137, XP010277151, ISBN: 0-8186-8436-4
  • [X] GROCHOWSKI, ET AL.: "Integrated Circuit Testing for Quality Assurance in Manufacturing: History, Current Status, and Future Trends", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, vol. 44, no. 8, August 1997 (1997-08-01), pages 610 - 633, XP011012685
  • [A] VARIYAM P N ET AL: "Test generation for comprehensive testing of linear analog circuits using transient response sampling", COMPUTER-AIDED DESIGN, 1997. DIGEST OF TECHNICAL PAPERS., 1997 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 9-13 NOV. 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 9 November 1997 (1997-11-09), pages 382 - 385, XP010261079, ISBN: 0-8186-8200-0
  • [A] CHAKRABARTI S ET AL: "Diagnostic test pattern generation for analog circuits using hierarchical models", VLSI DESIGN, 1999. PROCEEDINGS. TWELFTH INTERNATIONAL CONFERENCE ON GOA, INDIA 7-10 JAN. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 7 January 1999 (1999-01-07), pages 518 - 523, XP010319997, ISBN: 0-7695-0013-7
  • See references of WO 0070358A1

Designated contracting state (EPC)

DE

DOCDB simple family (publication)

WO 0070358 A1 20001123; AU 5442000 A 20001205; EP 1212626 A1 20020612; EP 1212626 A4 20060524

DOCDB simple family (application)

US 0013862 W 20000519; AU 5442000 A 20000519; EP 00939316 A 20000519