Global Patent Index - EP 1215813 B1

EP 1215813 B1 20061004 - Tuner for digital receiver with multiple input and multiple output channels

Title (en)

Tuner for digital receiver with multiple input and multiple output channels

Title (de)

Tuner für digitalen Empfänger mit mehreren Eingangskanälen und Ausgangskanälen

Title (fr)

Circuit d'accord pour récepteur numérique avec plusieurs canaux d'entrée et plusieurs canaux de sortie

Publication

EP 1215813 B1 20061004 (EN)

Application

EP 00403506 A 20001213

Priority

EP 00403506 A 20001213

Abstract (en)

[origin: EP1215813A1] The present invention teaches a compact and highly integrated multiple-channel digital tuner and receiver architecture, suitable for widespread field deployment, wherein each receiver demodulator channel may be remotely, automatically, dynamically, and economically configured for a particular cable, carrier frequency, and signaling baud-rate, from an option universe that includes a plurality of input cables, a plurality of carrier frequencies, and a plurality of available baud-rates. A multiple coax input, multiple channel output, digital tuner is partitioned into a multiple coax input digitizer portion (900) and a multiple channel output front-end portion (6000). The digitizer portion consists of N digitizers and accepts input signals from N coax cables (1800-1...1800-N) and digitizes them with respective A/D converters (930-1...930-N). The front-end portion (6000) consists of M front-ends and provides M channel outputs suitable for subsequent processing by M respective digital demodulators. In a first clock domain (1100), a fixed predetermined A/D sampling rate is chosen to provide oversampling of the inputs by a common integer multiple of all the symbol rates of interest. A plurality of other clock domains (1200,1300-1) operate at selectable sub-multiples of the first domain (1100) as required to deliver a constant number of symbol samples at the output of each front-end. At the input to each of the M front-ends is a respective input selector (2000-1...2000-M) coupled to each of the N streams of digitized input data followed by a digital signal scaler (3000-1...3000-M) that dynamically scales the selected incoming stream of digitized input data as a function of the signal power of the channel's associated carrier. <IMAGE>

IPC 8 full level

H03D 3/00 (2006.01); H04N 5/50 (2006.01); H04N 7/173 (2011.01); H04N 5/44 (2011.01)

CPC (source: EP US)

H03D 3/007 (2013.01 - EP US); H04B 1/0003 (2013.01 - EP US); H04B 1/406 (2013.01 - EP US); H04N 5/50 (2013.01 - EP US); H04N 7/17309 (2013.01 - EP US); H04N 21/4263 (2013.01 - EP US); H04N 21/4383 (2013.01 - EP US); H03D 3/006 (2013.01 - EP US); H04N 21/426 (2013.01 - EP US)

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

DOCDB simple family (publication)

EP 1215813 A1 20020619; EP 1215813 B1 20061004; AT E341854 T1 20061015; AU 2895402 A 20020624; DE 60031142 D1 20061116; DE 60031142 T2 20070823; US 2002150173 A1 20021017; US 2007019539 A1 20070125; US 2009268853 A1 20091029; US 7142620 B2 20061128; US 7570723 B2 20090804; US 8149970 B2 20120403; WO 0249264 A1 20020620

DOCDB simple family (application)

EP 00403506 A 20001213; AT 00403506 T 20001213; AU 2895402 A 20011210; DE 60031142 T 20001213; US 0147632 W 20011210; US 49164009 A 20090625; US 53635006 A 20060928; US 97403001 A 20011010