EP 1225627 B1 20090610 - Semiconductor integrated circuit device and manufacture method therefor
Title (en)
Semiconductor integrated circuit device and manufacture method therefor
Title (de)
Integrierter Halbleiterschaltkreis und zugehöriges Herstellungsverfahren
Title (fr)
Circuit intégré à semi-conducteur et son procédé de fabrication
Publication
Application
Priority
JP 2001015043 A 20010123
Abstract (en)
[origin: EP1225627A2] The object of the present invention is to prevent elements in a triple-well MOS transistor from being destroyed due to an increase in current consumption or a thermal runaway of a parasitic bipolar transistor. <??>In a triple-well NMOS transistor 311 comprising a P well area 22 formed within an N well area 28 and a MOSFET formed in the P well area 22, an impurity-diffused area 29 having a lower impurity concentration than an N<+> drain area 25 is formed close to the N<+> drain area 25, thereby restraining substrate current. The impurity concentration of the P well area 22 is increased to reduce the current gain of a parasitic bipolar transistor. To further reduce the current gain, a punch-through stopper area may be formed. The impurity concentration of the impurity-diffused area 29 is set to equal that of an N- LDD area 31 of a fine CMOS device integrated on the same substrate 1. These areas are formed during a single ion injection step. <IMAGE>
IPC 8 full level
H01L 21/8238 (2006.01); H01L 27/092 (2006.01)
CPC (source: EP US)
H01L 21/823814 (2013.01 - EP US); H01L 27/0921 (2013.01 - EP US)
Designated contracting state (EPC)
DE IT NL
DOCDB simple family (publication)
EP 1225627 A2 20020724; EP 1225627 A3 20050112; EP 1225627 B1 20090610; DE 60232563 D1 20090723; JP 2002222869 A 20020809; US 2002117713 A1 20020829; US 2003207509 A1 20031106; US 6809376 B2 20041026
DOCDB simple family (application)
EP 02250303 A 20020116; DE 60232563 T 20020116; JP 2001015043 A 20010123; US 43595603 A 20030512; US 5571702 A 20020123