EP 1225699 A2 20020724 - PLL circuit having a variable output frequency
Title (en)
PLL circuit having a variable output frequency
Title (de)
PLL-Schaltung mit veränderbarer Ausgangsfrequenz
Title (fr)
Circuit PLL à fréquence de sortie variable
Publication
Application
Priority
JP 2001001232 A 20010109
Abstract (en)
A phase locked loop (PLL) circuit includes a VCO (11) having a parallel resonant circuit including a first capacitance (C4) implemented by a reverse-biased diode and a second capacitance (C1 to C3) implemented by MOS capacitors. Upon lock-in of the oscillation frequency with respect to the reference frequency, whether the oscillation frequency has a deviation is examined based on the tune voltage controlling the first variable capacitance (C4). If a deviation is observed due to a temperature fluctuation etc., the control voltage for the second variable capacitance (C1 to C3) is corrected for compensating the deviation. <IMAGE>
IPC 1-7
IPC 8 full level
H03L 7/08 (2006.01); H03L 7/099 (2006.01); H03L 7/10 (2006.01); H03L 7/18 (2006.01); H03L 7/187 (2006.01); H03L 7/095 (2006.01)
CPC (source: EP KR US)
H03L 7/08 (2013.01 - KR); H03L 7/099 (2013.01 - EP US); H03L 7/104 (2013.01 - EP US); H03L 7/18 (2013.01 - EP US); H03L 7/095 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
EP 1225699 A2 20020724; EP 1225699 A3 20050406; EP 1225699 B1 20081231; CN 100550644 C 20091014; CN 1365190 A 20020821; DE 60230554 D1 20090212; JP 2002208857 A 20020726; JP 3414382 B2 20030609; KR 100415956 B1 20040124; KR 20020060097 A 20020716; US 2002089384 A1 20020711; US 6587005 B2 20030701
DOCDB simple family (application)
EP 02000138 A 20020104; CN 02101562 A 20020109; DE 60230554 T 20020104; JP 2001001232 A 20010109; KR 20020001185 A 20020109; US 2380401 A 20011221