Global Patent Index - EP 1226503 A2

EP 1226503 A2 20020731 - BUS SYSTEM FOR SIMULTANEOUS HANDLING OF VARIOUS MEMORY ACCESS PROCEDURES WITH A SYSTEM-ON-CHIP SOLUTION

Title (en)

BUS SYSTEM FOR SIMULTANEOUS HANDLING OF VARIOUS MEMORY ACCESS PROCEDURES WITH A SYSTEM-ON-CHIP SOLUTION

Title (de)

BUS-SYSTEM ZUR SIMULTANEN BEARBEITUNG VERSCHIEDENER SPEICHERZUGRIFFE BEI SYSTEM-ON-CHIP-LÖSUNGEN

Title (fr)

SYSTEME DE BUS PERMETTANT LE TRAITEMENT SIMULTANE DE DIFFERENTS ACCES A LA MEMOIRE AVEC DES SOLUTIONS DE SYSTEME SUR PUCE

Publication

EP 1226503 A2 20020731 (DE)

Application

EP 00981154 A 20001025

Priority

  • DE 0003765 W 20001025
  • DE 19952543 A 19991102

Abstract (en)

[origin: WO0133363A2] The invention relates to a data processing device for transmitting, receiving, processing and storing of data, comprising at least one central unit (1a...1c), at least one send and receive unit (2) and a first and a second memory unit (3a, 3b). The at least one central unit (1a...1c) and the send and receive unit (2) are users of the memory units (3a...3b), whereby an access device (4) is arranged with each memory unit, to control the random, simultaneous access of the two users (1a...1c, 2), such that a simultaneous access to both memory devices is possible.

IPC 1-7

G06F 13/00

IPC 8 full level

G06F 13/42 (2006.01)

CPC (source: EP)

G06F 13/4243 (2013.01)

Citation (search report)

See references of WO 0133363A2

Designated contracting state (EPC)

DE FR GB

DOCDB simple family (publication)

WO 0133363 A2 20010510; WO 0133363 A3 20011213; EP 1226503 A2 20020731

DOCDB simple family (application)

DE 0003765 W 20001025; EP 00981154 A 20001025