Global Patent Index - EP 1240583 A2

EP 1240583 A2 2002-09-18 - DUAL-MODE PROCESSOR

Title (en)

DUAL-MODE PROCESSOR

Title (de)

DUAL-MODUS-PROZESSOR

Title (fr)

PROCESSEUR BIMODAL

Publication

EP 1240583 A2 (EN)

Application

EP 00986569 A

Priority

  • US 0034458 W
  • US 47175499 A

Abstract (en)

[origin: WO0146800A2] A multiple-mode processing circuit, such as a dual-mode processor (5), operates in at least first and second modes according to a switch (10). When a mode is active, data transfer between the processor and a respective memory occurs. Thus, instructions from the memory can be executed at the processor, and the results can be stored in the respective memory. For example, first and second memories (14, 54) may be provided for the first and second modes (10, 50), respectively. The memories are separate, and no data transfer can occur between the memories directly or via the processor. The first mode (10) may be a secure mode for secure processing operations, such as providing conditional access for television programming services at a set-top subscriber terminal. The second mode (50) may be a non-secure mode, such as for providing any other application at the terminal, e.g., program guide, shop at home service, etc. In one embodiment, a data bus is provided for time-multiplexed transfer of data between the processor and the respective memories. In another embodiment, switching of individual internal registers and external elements such as address and data latches, is provided.

IPC 1-7 (main, further and additional classification)

G06F 9/00

IPC 8 full level (invention and additional information)

G06F 12/14 (2006.01); G06F 9/30 (2006.01); G06F 9/318 (2006.01); G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 21/71 (2013.01); G06F 21/74 (2013.01); G06F 21/79 (2013.01)

CPC (invention and additional information)

G06F 21/74 (2013.01); G06F 9/3012 (2013.01); G06F 9/30123 (2013.01); G06F 9/30189 (2013.01); G06F 9/3851 (2013.01); G06F 12/1433 (2013.01); G06F 21/71 (2013.01); G06F 21/79 (2013.01); G06F 2221/2105 (2013.01)

Citation (search report)

See references of WO 0146800A3

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

EPO simple patent family

WO 0146800 A2 20010628; WO 0146800 A3 20020725; AU 2278601 A 20010703; CA 2395645 A1 20010628; CN 1425157 A 20030618; EP 1240583 A2 20020918; JP 2003518287 A 20030603; MX PA02006214 A 20030128; TW 541466 B 20030711

INPADOC legal status


2007-05-02 [18D] APPLICATION DEEMED TO BE WITHDRAWN

- Effective date: 20061009

2002-09-18 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20020625

2002-09-18 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A2

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

2002-09-18 [AX] REQUEST FOR EXTENSION OF THE EUROPEAN PATENT TO:

- Free text: AL;LT;LV;MK;RO;SI