Global Patent Index - EP 1254479 A1

EP 1254479 A1 20021106 - WAFER BONDING TECHNIQUES TO MINIMIZE BUILT-IN STRESS OF SILICON MICROSTRUCTURES AND MICRO-MIRRORS

Title (en)

WAFER BONDING TECHNIQUES TO MINIMIZE BUILT-IN STRESS OF SILICON MICROSTRUCTURES AND MICRO-MIRRORS

Title (de)

TECHNIK ZUM ZUSAMMENFÜGEN VON SCHEIBEN UNTER MINIMIERUNG DES EINGEBAUTEN STRESSES VON SILIZIUM MIKROSTRUKTUREN UND MIKROSPIEGEL

Title (fr)

LIAGE DESTINE A MINIMISER LA CONTRAINTE INTEGREE DES MICROSTRUCTURES ET DES MICROMIROIRS EN SILICIUM

Publication

EP 1254479 A1 20021106 (EN)

Application

EP 01903124 A 20010118

Priority

  • US 0101758 W 20010118
  • US 17632500 P 20000118
  • US 71591600 A 20001116

Abstract (en)

[origin: WO0154176A1] A bonded wafer fabrication mechanism for a micro-mirror structure provides for oxidizing a device wafer instead of a handle wafer or splitting thermal oxidation processing between the device wafer and the handle wafer prior to etching. The flatness of mirrors in micro-mirror structures fabricated according to such a mechanism is substantially improved.

IPC 1-7

H01L 21/20; H01L 21/762

IPC 8 full level

H01L 21/20 (2006.01); H01L 21/762 (2006.01)

CPC (source: EP)

H01L 21/2007 (2013.01); H01L 21/76251 (2013.01)

Citation (search report)

See references of WO 0154176A1

Designated contracting state (EPC)

AT BE CH DE FR GB LI

DOCDB simple family (publication)

WO 0154176 A1 20010726; WO 0154176 A9 20030116; AU 3098201 A 20010731; CA 2397760 A1 20010726; EP 1254479 A1 20021106

DOCDB simple family (application)

US 0101758 W 20010118; AU 3098201 A 20010118; CA 2397760 A 20010118; EP 01903124 A 20010118