Global Patent Index - EP 1261120 A1

EP 1261120 A1 2002-11-27 - Power optimized input circuit

Title (en)

Power optimized input circuit

Title (de)

Leistungsoptimierte Eingangsschaltung

Title (fr)

Circuit d'entrée optimisé en puissance électrique

Publication

EP 1261120 A1 (DE)

Application

EP 02360135 A

Priority

DE 10125283 A

Abstract (en)

The arrangement has a first current source (ST1), a unit for electrical isolation, an intermediate resistance (RZ) and a second current source (ST2). The unit for electrical isolation and the intermediate resistance are both connected between the two current sources. Each current source contains a transistor (T1,T2), a resistor (RS1,RS2) and a Zener diode (S1,S2). AN Independent claim is also included for a parallel input/output unit for railway signaling.

Abstract (de)

Die erfindungsgemäße Eingangsschaltung beinhaltet zwei Stromquellen (ST1, ST2), einen ohmschen Zwischenwiderstand (Rz) und als Baugruppe zur galvanischen Trennung einen Opto-Koppler (O). Zwischenwiderstand (Rz) und Opto-Koppler (O) sind jeweils zwischen die beiden Stromquellen (ST1, ST2) geschaltet. Durch die Verwendung einer zweiten Stromquelle (ST2) anstelle eines ohmschen Vorwiderstands wird die Verlustleistung deutlich reduziert. <IMAGE>

IPC 1-7 (main, further and additional classification)

H02M 3/155; B60M 3/02; G05F 3/18

IPC 8 full level (invention and additional information)

G05F 3/18 (2006.01)

CPC (invention and additional information)

G05F 3/18 (2013.01)

Citation (search report)

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

EPO simple patent family

EP 1261120 A1 20021127; EP 1261120 B1 20041201; AT 284087 T 20041215; DE 10125283 A1 20021128

INPADOC legal status


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