EP 1269314 A2 20030102 - ARRANGEMENT AND METHOD FOR REDUCING THE PROCESSING TIME OF A DATA PROCESSING DEVICE
Title (en)
ARRANGEMENT AND METHOD FOR REDUCING THE PROCESSING TIME OF A DATA PROCESSING DEVICE
Title (de)
ANORDNUNG UND VERFAHREN ZUR REDUZIERUNG DER VERARBEITUNGSZEIT EINER DATENVERARBEITUNGSEINRICHTUNG
Title (fr)
DISPOSITIF ET PROCEDE VISANT A REDUIRE LE TEMPS DE TRAITEMENT D'UN DISPOSITIF DE TRAITEMENT DE DONNEES
Publication
Application
Priority
- DE 0101067 W 20010320
- DE 10015693 A 20000329
Abstract (en)
[origin: WO0173552A2] The present invention relates to a data processing device (1) comprising a processor (2) and a memory (3) which consists of a first memory region (4) and a second memory region (6). A first cache (5) is arranged for the first memory region (4) and a second cache (7) is arranged for the second memory region (6). The second cache (7) intermediately stores predetermined and selected subprograms, interrupt vectors (8) and interrupt handlers (9) in said second cache (7). Said subprograms, interrupt vectors (8) and interrupt handlers (9) are usually stored in the second memory region (6) which is a ROM memory or a RAM memory for instance. In an advantageous embodiment, displacement cycles do not take place in the second cache (7).
IPC 1-7
IPC 8 full level
G06F 12/0897 (2016.01)
CPC (source: EP)
G06F 12/0897 (2013.01)
Citation (search report)
See references of WO 0173552A2
Citation (examination)
JOURNAL ARTICLE: "EMBEDDED-CONTROL MIT RISC. ÖFLEXIBLE SYSTEM-DESIGNS MIT DEM SAB-R3000", ELEKTRONIK, vol. 40, no. 17, 20 August 1991 (1991-08-20), WEKA FACHZEITSCHRIFTENVERLAG, POING, DE, pages 66 - 72, XP000260939
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
DOCDB simple family (publication)
WO 0173552 A2 20011004; WO 0173552 A3 20020815; DE 10015693 A1 20011018; EP 1269314 A2 20030102
DOCDB simple family (application)
DE 0101067 W 20010320; DE 10015693 A 20000329; EP 01923523 A 20010320