EP 1341182 A2 20030903 - Semiconductor memory
Title (en)
Semiconductor memory
Title (de)
Halbleiterspeicher
Title (fr)
Mémoire à semicinducteurs
Publication
Application
Priority
JP 2002047956 A 20020225
Abstract (en)
A semiconductor memory is provided that comprises a plurality of memory cell arrays (ALY), each memory cell array (ALY) including bit lines (BL, /BL) and memory cells each constituted by a variable capacitor, the memory cell arrays (ALY) operating at mutually different timings. The bit lines (BL, /BL) of each memory cell array (ALY) are connected to bit lines (BL, /BL) of the other memory cell arrays (ALY) via connecting wires (CW). Accordingly, the actual capacitances of the bit lines (BL, /BL) are the capacitances of bit lines (BL, /BL) of that memory cell array (ALY) itself plus that of the other memory cell arrays (ALY) plus the capacitances of the connecting wires (CW). Therefore, when data is read from the memory cells, the variations in voltage of the bit lines (BL, /BL) caused by the capacitive division can be enlarged. Consequently, the read margin can be prevented from being degraded, and the manufacturing yield of semiconductor memories can be prevented from being degraded. Additionally, since the variations in voltage of the bit lines are enlarged, the data reading time can be shortened. <IMAGE>
IPC 1-7
IPC 8 full level
G11C 11/22 (2006.01); H10B 20/00 (2023.01)
CPC (source: EP KR US)
G11C 11/22 (2013.01 - EP KR US)
DOCDB simple family (publication)
EP 1341182 A2 20030903; EP 1341182 A3 20040512; EP 1341182 B1 20080305; CN 1306614 C 20070321; CN 1441497 A 20030910; DE 60225416 D1 20080417; JP 2003249628 A 20030905; JP 3936599 B2 20070627; KR 100823795 B1 20080421; KR 20030070525 A 20030830; TW I269296 B 20061221; US 2003161174 A1 20030828; US 6862204 B2 20050301
DOCDB simple family (application)
EP 02257329 A 20021022; CN 02150529 A 20021112; DE 60225416 T 20021022; JP 2002047956 A 20020225; KR 20020066032 A 20021029; TW 91124565 A 20021023; US 27715002 A 20021022