Global Patent Index - EP 1352420 A1

EP 1352420 A1 20031015 - INSULATING STRUCTURES OF BURIED LAYERS WITH BURIED TRENCHES AND METHOD FOR MAKING SAME

Title (en)

INSULATING STRUCTURES OF BURIED LAYERS WITH BURIED TRENCHES AND METHOD FOR MAKING SAME

Title (de)

ISOLIERENDE STRUKTUREN VERGRABENER SCHICHTEN MIT VERGRABENEN GRÄBEN UND VERFAHREN ZU IHRER HERSTELLUNG

Title (fr)

STRUCTURE D ISOLATION DE COUCHES ENTERREES PAR TRANCHEES ENTERREES, ET PROCEDE DE FABRICATION

Publication

EP 1352420 A1 20031015 (FR)

Application

EP 02710091 A 20020109

Priority

  • FR 0200055 W 20020109
  • FR 0100412 A 20010112

Abstract (en)

[origin: WO02056363A1] The invention concerns an integrated circuit semiconductor substrate comprising at least a dielectrically vertical buried trench and having a height at least five times more than its width, and an epitaxial semiconductor layer (6) covering said trench laterally separating two regions (4, 5). The invention is applicable to MOS, CMOS and BICMOS technologies. The invention also concerns a method for making said substrate.

IPC 1-7

H01L 21/762; H01L 21/74; H01L 27/06; H01L 21/8249; H01L 21/8238

IPC 8 full level

H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/8222 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/8248 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 27/08 (2006.01); H01L 27/092 (2006.01)

CPC (source: EP US)

H01L 21/76224 (2013.01 - EP US); H01L 21/823481 (2013.01 - EP US); H01L 21/8249 (2013.01 - EP US)

Citation (search report)

See references of WO 02056363A1

Citation (examination)

Designated contracting state (EPC)

AT BE CH CY DE FR GB IT LI

DOCDB simple family (publication)

WO 02056363 A1 20020718; EP 1352420 A1 20031015; FR 2819629 A1 20020719; FR 2819629 B1 20030704; JP 2004527102 A 20040902; US 2004075107 A1 20040422; US 6812541 B2 20041102

DOCDB simple family (application)

FR 0200055 W 20020109; EP 02710091 A 20020109; FR 0100412 A 20010112; JP 2002556931 A 20020109; US 25053803 A 20031202