EP 1382975 B1 20080102 - Method of generating a test pattern for the simulation and/or test of the layout of an integrated circuit
Title (en)
Method of generating a test pattern for the simulation and/or test of the layout of an integrated circuit
Title (de)
Verfahren zur Erzeugung eines Testmusters für die Simulation und/oder Prüfung des Layouts einer integrierten Schaltung
Title (fr)
Procédé de génération de motifs d'essai pour la simulation et/ou essai d'un circuit intégré
Publication
Application
Priority
EP 02090271 A 20020719
Abstract (en)
[origin: EP1382975A1] There is provided a method of generating a test pattern for the simulation and/or test of the layout of an integrated circuit, the method comprising the steps of: (a) generating a set of test patterns on a random basis; (b) applying the set of test patterns to the integrated circuit using automatic test equipment (ATE); (c) determining the outputs of the integrated circuit; (d) processing the outputs to determine whether predetermined test criteria are met; (e) depending on the determination in step (d), generating a new set of test patterns on the basis of the set of test patterns employed in step (c) using a genetic algorithm. Accordingly, the method employs a genetic algorithm (optimization method) to optimize a set of random patterns based on measurements using an ATE. Thereby, a set of worst case noise patterns can be selected automatically. <IMAGE>
IPC 8 full level
G01R 31/3183 (2006.01)
CPC (source: EP US)
G01R 31/318371 (2013.01 - EP US)
Citation (examination)
WO 03107019 A2 20031224 - UNIV STRATHCLYDE [GB], et al
Designated contracting state (EPC)
DE GB IE
DOCDB simple family (publication)
EP 1382975 A1 20040121; EP 1382975 B1 20080102; DE 60224378 D1 20080214; DE 60224378 T2 20090102; US 2004034838 A1 20040219; US 6993735 B2 20060131
DOCDB simple family (application)
EP 02090271 A 20020719; DE 60224378 T 20020719; US 62306703 A 20030718