EP 1384259 A2 20040128 - METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
Title (en)
METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
Title (de)
HERSTELLUNGSVERFAHREN FÜR EINE INTEGRIERTE SCHALTUNG
Title (fr)
PROCEDE DE PRODUCTION D'UN CIRCUIT INTEGRE
Publication
Application
Priority
- DE 10120929 A 20010430
- EP 0204067 W 20020411
Abstract (en)
[origin: WO02089202A2] The invention relates to a method for the production of an integrated circuit, comprising the following steps: a substrate (1) is provided with at least one first, second and third gate stack (GS1, GS2, GS3) of approximately the same height on the surface of said substrate, a common active area (60) being provided on the surface of the substrate in said substrate (1) between the first and second gate stack (GS1, GS2); a first insulating layer (70) is provided in order to cover the embedding of the first, second and third gate stack (GS1, GS2, GS3); the upper side of a gate connection (20) of the third gate stack (GS3) is uncovered; a second insulating layer (80) is provided in order to cover the upper side of a gate connection (20); a mask (M2) is provided on the resulting structure having a first opening (F2a) above the uncovered upper side of the gate connection (20) of the third gate stack (GS3), a second opening (F2b) above the substrate (1) between the third and second gate stack (GS3, GS2) and a third opening (F2c) above the common active area (60), partially overlapping the first and second gate stack (GS1, GS2), and simultaneously forming a first, second and third contact hole (KB, KS, KG) using said mask (32) in an etching process, the first contact hole (KB) uncovering the common active area (60) on the surface of the substrate between the first and second gate stack (GS1, GS2), the second contact hole (KS) uncovering the surface of the substrate between the second and third gate stack (GS2, GS2) and the third contact hole (KG) uncovering the upper side of the gate connection (20) of the third gate stack (GS3).
IPC 1-7
IPC 8 full level
H01L 21/283 (2006.01); H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 21/4763 (2006.01); H01L 21/60 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 21/8242 (2006.01); H01L 21/8246 (2006.01); H01L 21/8247 (2006.01); H01L 27/115 (2006.01); H01L 27/11521 (2017.01)
CPC (source: EP KR US)
H01L 21/76816 (2013.01 - EP US); H01L 21/76897 (2013.01 - EP US); H01L 21/82 (2013.01 - KR); H10B 41/30 (2023.02 - EP US); H10B 69/00 (2023.02 - EP US)
Citation (search report)
See references of WO 02089202A2
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
DOCDB simple family (publication)
WO 02089202 A2 20021107; WO 02089202 A3 20030220; DE 10120929 A1 20021031; EP 1384259 A2 20040128; KR 100563789 B1 20060327; KR 20040015210 A 20040218; TW 571393 B 20040111; US 2004147107 A1 20040729; US 6984578 B2 20060110
DOCDB simple family (application)
EP 0204067 W 20020411; DE 10120929 A 20010430; EP 02737948 A 20020411; KR 20037014172 A 20031030; TW 91105657 A 20020322; US 47635503 A 20031030