EP 1388865 A3 20040331 - Semiconductor memory device and control method therefor
Title (en)
Semiconductor memory device and control method therefor
Title (de)
Halbleiterspeicher und dessen Steuerungsverfahren
Title (fr)
Dispositif de mémoire à semiconducteurs et sa méthode de commande
Publication
Application
Priority
JP 2002231644 A 20020808
Abstract (en)
[origin: EP1388865A2] Disclosed is a semiconductor memory device which shortens an external access time when there is contention between an external access and an internal access. The semiconductor memory device includes an arbiter (13) which receives a first entry signal for entering a first access mode (external access) and a second entry signal for entering a second access mode (internal access) and determines priority of the first and second access modes in accordance with an order of receipt of the first and second entry signals. The arbiter (13) sequentially generates a first mode trigger signal corresponding to the first entry signal and a second mode trigger signal corresponding to the second entry signal in accordance with the determined priority. The arbiter (13) executes the first access mode by priority over the second access mode when the arbiter is supplied with the first entry signal with a predetermined period after the second access mode has been determined to have priority. <IMAGE>
IPC 1-7
IPC 8 full level
G01R 31/28 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G11C 11/403 (2006.01); G11C 11/406 (2006.01); G11C 29/08 (2006.01); G11C 29/50 (2006.01)
CPC (source: EP KR US)
G11C 11/406 (2013.01 - EP KR US); G11C 11/40603 (2013.01 - EP US); G11C 29/50 (2013.01 - EP US); G11C 29/50012 (2013.01 - EP US); G11C 29/50016 (2013.01 - EP US); G11C 11/401 (2013.01 - EP US)
Citation (search report)
- [XAY] US 2002057607 A1 20020516 - MIZUGAKI KOICHI [JP], et al
- [XAY] US 2001017811 A1 20010830 - IKEDA HITOSHI [JP], et al
- [XA] GB 2265035 A 19930915 - APPLE COMPUTER [US]
- [A] US 2002024865 A1 20020228 - FUJIEDA WAICHIRO [JP], et al
- [A] US 2001048623 A1 20011206 - TANIZAKI TETSUSHI [JP], et al
- [A] PATENT ABSTRACTS OF JAPAN vol. 1998, no. 01 30 January 1998 (1998-01-30)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
DOCDB simple family (publication)
EP 1388865 A2 20040211; EP 1388865 A3 20040331; EP 1388865 B1 20130828; CN 100346422 C 20071031; CN 100555447 C 20091028; CN 101051525 A 20071010; CN 101051525 B 20120704; CN 101055761 A 20071017; CN 101055761 B 20120620; CN 101055762 A 20071017; CN 1480949 A 20040310; JP 2004071097 A 20040304; JP 4188640 B2 20081126; KR 100919270 B1 20090930; KR 20040014274 A 20040214; TW 200403685 A 20040301; TW I223279 B 20041101; US 2004027882 A1 20040212; US 7287142 B2 20071023
DOCDB simple family (application)
EP 03016890 A 20030724; CN 03149659 A 20030805; CN 200710106806 A 20030805; CN 200710106807 A 20030805; CN 200710106808 A 20030805; JP 2002231644 A 20020808; KR 20030054009 A 20030805; TW 92120220 A 20030724; US 63475803 A 20030806