EP 1407416 A2 20040414 - MULTIPLIER CIRCUIT
Title (en)
MULTIPLIER CIRCUIT
Title (de)
MULTIPLIZIERERSCHALTUNG
Title (fr)
CIRCUIT MULTIPLICATEUR
Publication
Application
Priority
- DE 0202525 W 20020710
- DE 10134754 A 20010717
Abstract (en)
[origin: WO03009078A2] The invention relates to a multiplier circuit comprising a multiplier core that contains two cross-coupled transistor pairs (2, 3; 4, 5). According to the invention, a first and a second signal source (10, 11, 13, 14), which are controlled by a first or second signal that is to be multiplied, are respectively connected to control inputs of the transistors (2 to 5) of the multiplier core for inverting the current between the transistor pairs (2, 3; 4, 5), or in a differentiating manner between the transistors (2, 4; 3, 5) of the differential amplifiers. The high degree of symmetry that can be achieved for the input gates of the circuit permits a particularly precise multiplication with excellent linearity. The inventive multiplier can be used, for example, as a high-frequency mixer circuit or as a 90 DEG phase-detector circuit.
IPC 1-7
IPC 8 full level
G06G 7/163 (2006.01)
CPC (source: EP US)
G06G 7/163 (2013.01 - EP US)
Citation (search report)
See references of WO 03009078A2
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR
DOCDB simple family (publication)
WO 03009078 A2 20030130; WO 03009078 A3 20030403; DE 10134754 A1 20030206; DE 50203287 D1 20050707; EP 1407416 A2 20040414; EP 1407416 B1 20050601; US 2004155694 A1 20040812; US 7026857 B2 20060411
DOCDB simple family (application)
DE 0202525 W 20020710; DE 10134754 A 20010717; DE 50203287 T 20020710; EP 02753008 A 20020710; US 48401004 A 20040115