Title (en)

INTEGRATED CIRCUIT COMPRISING DRAM MEMORY CELLS AND THE PRODUCTION METHOD THEREFOR

Title (de)

INTEGRIERTE SCHALTUNG MIT DRAM-SPEICHERZELLEN UND HERSTELLUNGSVERFAHREN DAFÜR

Title (fr)

CIRCUIT INTEGRE COMPRENANT DES CELLULES MEMOIRE DRAM ET PROCEDE DE FABRICATION

Publication

EP 1425794 A1 20040609 (FR)

Application

EP 02794817 A 20020814

Priority

• FR 0202886 W 20020814
• FR 0110866 A 20010816

Abstract (en)

[origin: US2003034821A1] There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

IPC 1-7

H01L 21/8242

IPC 8 full level

H01L 21/28 (2006.01); H01L 21/3205 (2006.01); H01L 21/768 (2006.01); H01L 23/52 (2006.01); H10B 12/00 (2023.01)

CPC (source: EP US)

H10B 12/033 (2023.02 - EP US); H10B 12/48 (2023.02 - EP US); H10B 12/485 (2023.02 - EP US)

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR

DOCDB simple family (publication)

US 2003034821 A1 20030220; US 6958505 B2 20051025; EP 1425794 A1 20040609; FR 2828766 A1 20030221; FR 2828766 B1 20040116; JP 2005500694 A 20050106; WO 03017361 A1 20030227

DOCDB simple family (application)

US 95592601 A 20010918; EP 02794817 A 20020814; FR 0110866 A 20010816; FR 0202886 W 20020814; JP 2003522166 A 20020814