Global Patent Index - EP 1439522 A3

EP 1439522 A3 2009-02-25 - Frame buffer control circuit

Title (en)

Frame buffer control circuit

Title (de)

Bildspeicherüberwachungssystem

Title (fr)

Circuit de contrôle d'une mémoire de trame

Publication

EP 1439522 A3 (DE)

Application

EP 04000243 A

Priority

DE 10301494 A

Abstract (en)

[origin: EP1439522A2] An image store (100) holds image data (ID). A control device (110) has a receiver (120) for picking up ID. An interface (130) transfers cycles of ID received to the image store, from where it calls up stored images. An output device (140) sends recalled ID to a display device (190). A monitoring device (150) checks the cyclic transfer of ID between the interface and the image store. An Independent claim is also included for a method for monitoring/checking images on plasma/thin film transistor (TFT) screens.

IPC 8 full level (invention and additional information)

G09G 5/39 (2006.01); G09G 5/393 (2006.01); G09G 3/00 (2006.01)

CPC (invention and additional information)

G09G 5/393 (2013.01); G09G 5/39 (2013.01); G09G 3/006 (2013.01)

Citation (search report)

[A] US 4839638 A 19890613 - KOSLAR MANFRED [DE], et al

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

Designated extension state (EPC)

AL LT LV MK

DOCDB simple family

EP 1439522 A2 20040721; EP 1439522 A3 20090225; DE 10301494 B3 20040826