Global Patent Index - EP 1456872 A1

EP 1456872 A1 20040915 - METHOD FOR DEPOSITING III-V SEMICONDUCTOR LAYERS ON A NON III-V SUBSTRATE

Title (en)

METHOD FOR DEPOSITING III-V SEMICONDUCTOR LAYERS ON A NON III-V SUBSTRATE

Title (de)

VERFAHREN ZUM ABSCHEIDEN VON III-V-HALBLEITERSCHICHTEN AUF EINEM NICHT-III-V-SUBSTRAT

Title (fr)

PROCEDE DE DEPOT DE COUCHES DE SEMI-CONDUCTEURS DES GROUPES III ET V SUR UN SUBSTRAT NE FAISANT PAS PARTIE DES GROUPES III ET V

Publication

EP 1456872 A1 20040915 (DE)

Application

EP 02792976 A 20021211

Priority

  • DE 10163715 A 20011221
  • DE 10206751 A 20020219
  • EP 0214096 W 20021211

Abstract (en)

[origin: WO03054939A1] The invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate, especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of an essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering or approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.

IPC 1-7

H01L 21/203; C30B 25/04; C30B 25/08

IPC 8 full level

C30B 25/02 (2006.01); C30B 25/18 (2006.01); H01L 21/20 (2006.01); H01L 21/205 (2006.01)

CPC (source: EP US)

C30B 25/02 (2013.01 - EP US); C30B 25/18 (2013.01 - EP US); C30B 29/40 (2013.01 - EP US); C30B 29/403 (2013.01 - EP US); H01L 21/0237 (2013.01 - EP US); H01L 21/02381 (2013.01 - EP US); H01L 21/0242 (2013.01 - EP US); H01L 21/02458 (2013.01 - EP US); H01L 21/02463 (2013.01 - EP US); H01L 21/02502 (2013.01 - EP US); H01L 21/02538 (2013.01 - EP US); H01L 21/02639 (2013.01 - EP US); H01L 21/02647 (2013.01 - EP US)

Citation (search report)

See references of WO 03054939A1

Citation (examination)

  • WO 0057460 A1 20000928 - MITSUBISHI CABLE IND LTD [JP], et al & EP 1178523 A1 20020206 - MITSUBISHI CABLE IND LTD [JP]
  • EP 1111663 A2 20010627 - NITRIDE SEMICONDUCTORS CO LTD [JP]
  • SAKAI S. ET AL: "A new method of reducing dislocation density in GaN layer grown on sapphire substrate by MOVPE", JOURNAL OF CRYSTAL GROWTH, vol. 221, 1 December 2000 (2000-12-01), pages 334 - 337, XP004226879

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR

DOCDB simple family (publication)

WO 03054939 A1 20030703; AU 2002358678 A1 20030709; EP 1456872 A1 20040915; JP 2005513799 A 20050512; TW 561526 B 20031111; US 2005022725 A1 20050203; US 7128786 B2 20061031

DOCDB simple family (application)

EP 0214096 W 20021211; AU 2002358678 A 20021211; EP 02792976 A 20021211; JP 2003555567 A 20021211; TW 91124715 A 20021024; US 87291404 A 20040621