EP 1512150 B1 20100901 - MEMORY ARRAY HAVING 2T MEMORY CELLS
Title (en)
MEMORY ARRAY HAVING 2T MEMORY CELLS
Title (de)
SPEICHERMATRIX MIT "2-TRANSISTOREN"-SPEICHERZELLEN
Title (fr)
MATRICE MEMOIRE AYANT DES CELLULES MEMOIRE 2T
Publication
Application
Priority
- EP 03722939 A 20030509
- EP 02077100 A 20020528
- IB 0301931 W 20030509
Abstract (en)
[origin: WO03100788A2] The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the present invention proposes a memory array having a plurality of memory cells each comprising:- a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and - a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.
IPC 8 full level
G11C 11/00 (2006.01); G11C 11/405 (2006.01); G11C 11/404 (2006.01); G11C 11/412 (2006.01)
CPC (source: EP US)
G11C 11/404 (2013.01 - EP US)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 03100788 A2 20031204; WO 03100788 A3 20040226; AT E479990 T1 20100915; AU 2003230096 A1 20031212; AU 2003230096 A8 20031212; CN 100541659 C 20090916; CN 1656565 A 20050817; DE 60333998 D1 20101014; EP 1512150 A2 20050309; EP 1512150 B1 20100901; JP 2005527931 A 20050915; TW 200403674 A 20040301; TW I289305 B 20071101; US 2005157533 A1 20050721; US 7038943 B2 20060502
DOCDB simple family (application)
IB 0301931 W 20030509; AT 03722939 T 20030509; AU 2003230096 A 20030509; CN 03812010 A 20030509; DE 60333998 T 20030509; EP 03722939 A 20030509; JP 2004508351 A 20030509; TW 92114054 A 20030523; US 51594104 A 20041123