EP 1537476 A2 20050608 - SYSTEM AND METHOD FOR EXECUTING BRANCH INSTRUCTIONS IN A VLIW PROCESSOR
Title (en)
SYSTEM AND METHOD FOR EXECUTING BRANCH INSTRUCTIONS IN A VLIW PROCESSOR
Title (de)
SYSTEM UND VERFHAREN ZUR AUSFÜHRUNG VON VERZWEIGUNGSBEFEHLEN IN EINEM VLIW PROZESSOR
Title (fr)
SYSTEME ET PROCEDE FAISANT APPEL A DES ELEMENTS DE TRAITEMENT A LATENCE DE BRANCHEMENT DIFFERENTIELLE
Publication
Application
Priority
- US 0324121 W 20030731
- US 21509502 A 20020808
Abstract (en)
[origin: US2004030872A1] The invention is a system and method for executing a program that comprises a plurality of basic blocks on a computer system that comprises a plurality of processing elements. The invention generates a branch instruction by one processing element of the plurality of processing elements, sends the branch instruction to the plurality of processing elements. The invention then independently branches to a target of the branch instruction by each of the processing elements of the plurality of processing elements when each processing element receives the sent branch instruction. At least one processing element of the plurality of processing elements receives the branch instruction at a time later than another processing element of the plurality of processing elements.
IPC 1-7
IPC 8 full level
G06F 9/38 (2006.01); G06F 15/00 (2006.01)
CPC (source: EP US)
G06F 9/3836 (2013.01 - EP US); G06F 9/3858 (2023.08 - EP); G06F 9/3887 (2013.01 - EP US)
Citation (search report)
See references of WO 2004015562A2
Designated contracting state (EPC)
DE
DOCDB simple family (publication)
US 2004030872 A1 20040212; US 7000091 B2 20060214; AU 2003268043 A1 20040225; AU 2003268043 A8 20040225; EP 1537476 A2 20050608; JP 2005535963 A 20051124; JP 3896136 B2 20070322; WO 2004015562 A2 20040219; WO 2004015562 A3 20041118
DOCDB simple family (application)
US 21509502 A 20020808; AU 2003268043 A 20030731; EP 03748994 A 20030731; JP 2004527707 A 20030731; US 0324121 W 20030731