EP 1550059 A2 20050706 - A SYSTEM AND METHOD FOR REDUCING WIRE DELAY OR CONGESTION DURING SYNTHESIS OF HARDWARE SOLVERS
Title (en)
A SYSTEM AND METHOD FOR REDUCING WIRE DELAY OR CONGESTION DURING SYNTHESIS OF HARDWARE SOLVERS
Title (de)
SYSTEM UND METHODE ZUR REDUZIERUNG VON LEITUNGSVERZÖGERUNG ODER ÜBERLASTUNG BEI DER SYNTHESE VON HARDWARE-SOLVERN
Title (fr)
SYSTEME ET PROCEDE PERMETTANT DE REDUIRE LE RETARD OU L'ENCOMBREMENT DE L'ACHEMINEMENT PENDANT LA SYNTHESE DE RESOLVANTS MATERIELS
Publication
Application
Priority
- US 0331619 W 20031003
- US 26671902 A 20021007
Abstract (en)
[origin: US2004068331A1] One embodiment of the invention is a method for producing a hardware solver for intermediate code comprising analyzing intermediate code for at least one instantiation that may cause at least one of wire delay and congestion in the solver, forming compensation for the at least one instantiation, and forming the solver in accordance with the compensation.
IPC 1-7
IPC 8 full level
G06F 17/50 (2006.01)
CPC (source: EP US)
G06F 30/30 (2020.01 - EP US); G06F 30/392 (2020.01 - EP US)
Citation (search report)
See references of WO 2004034291A2
Designated contracting state (EPC)
DE
DOCDB simple family (publication)
US 2004068331 A1 20040408; US 7107568 B2 20060912; AU 2003282708 A1 20040504; AU 2003282708 A8 20040504; DE 60318086 D1 20080124; DE 60318086 T2 20081204; EP 1550059 A2 20050706; EP 1550059 B1 20071212; JP 2006502502 A 20060119; WO 2004034291 A2 20040422; WO 2004034291 A3 20040722; WO 2004034291 A9 20060526
DOCDB simple family (application)
US 26671902 A 20021007; AU 2003282708 A 20031003; DE 60318086 T 20031003; EP 03774593 A 20031003; JP 2004543399 A 20031003; US 0331619 W 20031003