Global Patent Index - EP 1554651 A4

EP 1554651 A4 20071031 - METHOD AND APPARATUS FOR HIGH SPEED CROSS-THREAD INTERRUPTS IN A MULTITHREADED PROCESSOR

Title (en)

METHOD AND APPARATUS FOR HIGH SPEED CROSS-THREAD INTERRUPTS IN A MULTITHREADED PROCESSOR

Title (de)

VERFAHREN UND VORRICHTUNG FÜR SCHNELLE CROSS-THREAD-INTERRUPTS IN EINEM MULTITHREAD-PROZESSOR

Title (fr)

PROCEDE ET APPAREIL POUR DES INTERRUPTIONS DE FILIERES CROISEES A VITESSE ELEVEE DANS UN PROCESSEUR DE TRAITEMEMT MULTIFILIERE

Publication

EP 1554651 A4 20071031 (EN)

Application

EP 03776329 A 20031010

Priority

  • US 0332322 W 20031010
  • US 41845502 P 20021015
  • US 40417503 A 20030401

Abstract (en)

[origin: US2004073910A1] A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread to a destination thread. The interrupt controller in an illustrative embodiment receives a request for delivery of the cross-thread interrupt to the destination thread, determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier to control delivery of the cross-thread interrupt to the destination thread if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register of the multithreaded processor. The flag and enable registers may be implemented within the interrupt controller.

IPC 1-7

G06F 9/46; G06F 13/24

IPC 8 full level

G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 13/24 (2006.01); G06F 15/163 (2006.01)

IPC 8 main group level

G06F (2006.01)

CPC (source: EP KR US)

G06F 9/30101 (2013.01 - EP US); G06F 9/3851 (2013.01 - EP KR US); G06F 9/46 (2013.01 - KR); G06F 9/4812 (2013.01 - EP US)

Citation (search report)

  • [A] US 2002083252 A1 20020627 - ARMSTRONG WILLIAM JOSEPH [US], et al
  • [A] WO 0070482 A1 20001123 - XSTREAM LOGIC INC [US]
  • [A] INTEL CORPORATION: "8259A PROGRAMMABLE INTERRUPT CONTROLLER", INTERNET CITATION, December 1988 (1988-12-01), pages 1 - 24, XP002451563, Retrieved from the Internet <URL:http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf> [retrieved on 20070820]

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

DOCDB simple family (publication)

US 2004073910 A1 20040415; US 6971103 B2 20051129; AU 2003284098 A1 20040504; AU 2003284098 A8 20040504; EP 1554651 A2 20050720; EP 1554651 A4 20071031; EP 2306313 A1 20110406; JP 2006503385 A 20060126; KR 101002911 B1 20101220; KR 20050050126 A 20050527; WO 2004036354 A2 20040429; WO 2004036354 A3 20041118

DOCDB simple family (application)

US 40417503 A 20030401; AU 2003284098 A 20031010; EP 03776329 A 20031010; EP 10010949 A 20031010; JP 2005501397 A 20031010; KR 20057006201 A 20031010; US 0332322 W 20031010