EP 1571705 A3 20060104 - Process of making a semiconductor structure on a substrate
Title (en)
Process of making a semiconductor structure on a substrate
Title (de)
Verfahren zur Herstellung einer Hableiterstruktur auf einem Substrat
Title (fr)
Réalisation d'une entité en matériau semiconducteur sur substrat
Publication
Application
Priority
- FR 0402080 A 20040301
- US 86319304 A 20040607
Abstract (en)
[origin: EP1571705A2] A semiconductor entity is produced by supplying sufficient energy to detach a portion of a thin layer from a donor substrate located at a motif and to rupture bonds within the thin layer. The energy is insufficient to rupture the bond at the bonding interface. Production of a semiconductor entity involves providing a donor substrate (10) having a zone of weakness (15) at a predetermined depth to define a thin layer. The donor substrate includes a bonding interface. A receiver substrate (20) that includes at least one motif (22) on its surface is provided. The donor substrate is bonded at the bonding interface to the motif on the receiver substrate. Sufficient energy is supplied to detach a portion of the thin layer from the donor substrate located at the motif and to rupture bonds within the thin layer to form the semiconductor entity. The energy is insufficient to rupture the bond at the bonding interface. An independent claim is also included for a wafer comprising a first substrate including at least one projecting motif, and a second substrate bonded to the projecting motif. The second substrate further comprises a zone of weakness that defines a thin layer.
IPC 8 full level
H01L 21/02 (2006.01); H01L 21/20 (2006.01); H01L 21/301 (2006.01); H01L 21/762 (2006.01); H01L 33/00 (2006.01); H01L 33/48 (2010.01); H01S 5/022 (2006.01)
CPC (source: EP US)
H01L 21/76254 (2013.01 - EP US); H01L 2221/68318 (2013.01 - EP US)
Citation (search report)
- [Y] EP 1213748 A2 20020612 - SHARP KK [JP]
- [A] US 5559043 A 19960924 - BRUEL MICHEL [FR]
- [A] WO 02071475 A1 20020912 - COMMISSARIAT ENERGIE ATOMIQUE [FR], et al
- [Y] CELLER G K ET AL: "Frontiers of silicon-on-insulator", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 93, no. 9, 1 May 2003 (2003-05-01), pages 4955 - 4978, XP012059484, ISSN: 0021-8979
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
EP 1571705 A2 20050907; EP 1571705 A3 20060104; JP 2005311307 A 20051104; JP 4818618 B2 20111116; US 2007104240 A1 20070510; US 7439160 B2 20081021
DOCDB simple family (application)
EP 05290392 A 20050222; JP 2005056052 A 20050301; US 61702506 A 20061228