Global Patent Index - EP 1573605 A4

EP 1573605 A4 20060816 - METHOD, SYSTEM, AND ARTICLE OF MANUFACTURE FOR IMPLEMENTING METAL-FILL

Title (en)

METHOD, SYSTEM, AND ARTICLE OF MANUFACTURE FOR IMPLEMENTING METAL-FILL

Title (de)

VERFAHREN, SYSTEM UND HERSTELLUNGSARTIKELZUR IMPLEMENTIERUNG EINER METALLFÜLLUNG

Title (fr)

PROCEDE, SYSTEME ET ARTICLE DESTINES A LA MISE EN OEUVRE D'UNE TECHNIQUE DE REMPLISSAGE METALLIQUE

Publication

EP 1573605 A4 20060816 (EN)

Application

EP 03786859 A 20031119

Priority

  • US 0336989 W 20031119
  • US 30054402 A 20021119
  • US 30071502 A 20021119
  • US 30072202 A 20021119
  • US 30072402 A 20021119

Abstract (en)

[origin: WO2004047001A2] Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

IPC 1-7

G06F 17/50

IPC 8 full level

G06F 17/50 (2006.01)

IPC 8 main group level

G06K (2006.01)

CPC (source: EP)

G06F 30/39 (2020.01)

Citation (search report)

  • [A] US 6093631 A 20000725 - JASO MARK A [US], et al
  • [A] US 6305000 B1 20011016 - PHAN NGHIA VAN [US], et al
  • [A] US 5923563 A 19990713 - LAVIN MARK A [US], et al
  • [A] US 5763955 A 19980609 - FINDLEY PAUL RAJ [US], et al
  • [XP] US 2002199162 A1 20021226 - RAMASWAMY S RAM [US], et al
  • [XA] KAHNG A B ET AL: "FILLING ALGORITHMS AND ANALYSES FOR LAYOUT DENSITY CONTROL", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 18, no. 4, April 1999 (1999-04-01), pages 445 - 462, XP002370281, ISSN: 0278-0070
  • [XA] STINE B E ET AL: "THE PHYSICAL AND ELECTRICAL EFFECTS OF METAL-FILL PATTERNING PROCTICES FOR OXIDE CHEMICAL-MECHANICAL POLISHING PROCESSES", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 45, no. 3, March 1998 (1998-03-01), pages 665 - 679, XP000738545, ISSN: 0018-9383
  • [A] RUIQI TIAN ET AL: "Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS IEEE USA, vol. 20, no. 7, July 2001 (2001-07-01), pages 902 - 910, XP002370282, ISSN: 0278-0070
  • [A] YU CHEN ET AL: "Area fill synthesis for uniform layout density", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 21, no. 10, August 2002 (2002-08-01), pages 1132 - 1147, XP002309863, ISSN: 0278-0070
  • [AP] NELSON M ET AL: "Optimizing pattern fill for planarity and parasitic capacitance", ADVANCED SEMICONDUCTOR MANUFACTURING, 2004. ASMC '04. IEEE CONFERENCE AND WORKSHOP BOSTON, MA, USA 4-6 MAY 2004, PISCATAWAY, NJ, USA,IEEE, US, 4 May 2004 (2004-05-04), pages 115 - 118, XP010768975, ISBN: 0-7803-8312-5
  • [X] KAHNG A B ET AL: "Filling and slotting: analysis and algorithms", 1998, ISPD-98. 1998 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN ACM NEW YORK, NY, USA, pages 1 - 8, XP002385851, Retrieved from the Internet <URL:http://vlsicad.ucsd.edu/Publications/Conferences/c75.pdf> [retrieved on 20060619]
  • [X] KAHNG ANDREW B: "IC layout and manufacturability: Critical links and design flow implications", 1999, pages 1 - 7, XP002385852, Retrieved from the Internet <URL:http://ieeexplore.ieee.org/iel4/6007/16057/00745132.pdf?isnumber=&arnumber=745132> [retrieved on 20060619]
  • [X] YU CHEN ET AL: "Area Fill Synthesis for Uniform Layout Density", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 21, no. 10, October 2002 (2002-10-01), pages 1132 - 1147, XP011070638, ISSN: 0278-0070
  • [A] RANDAL E BRYANT ET AL: "Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI", PROCEEDINGS OF THE IEEE, IEEE. NEW YORK, US, vol. 89, no. 3, March 2001 (2001-03-01), pages 341 - 365, XP011044482, ISSN: 0018-9219
  • See references of WO 2004047001A2

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

DOCDB simple family (publication)

WO 2004047001 A2 20040603; WO 2004047001 A3 20040923; AU 2003295659 A1 20040615; AU 2003295659 A8 20040615; EP 1573605 A2 20050914; EP 1573605 A4 20060816; TW 200417874 A 20040916; TW I354901 B 20111221

DOCDB simple family (application)

US 0336989 W 20031119; AU 2003295659 A 20031119; EP 03786859 A 20031119; TW 92132437 A 20031119