EP 1629622 A2 20060301 - MARGIN TEST METHODS AND CIRCUITS
Title (en)
MARGIN TEST METHODS AND CIRCUITS
Title (de)
SPIELRAUMTEST-VERFAHREN UND -SCHALTKREISE
Title (fr)
PROCEDES ET CIRCUITS D'ESSAI DE MARGES
Publication
Application
Priority
- US 2004015895 W 20040520
- US 44146103 A 20030520
- US 81560404 A 20040331
- US 84926404 A 20040518
Abstract (en)
[origin: WO2004105334A2] Described are methods and circuits for margin testing digital receivers. Some embodiments prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing, while other embodiments rely upon the statistics of sampled data to explore the margin characteristics of received data.
IPC 1-7
IPC 8 full level
H04L 1/20 (2006.01); H04L 1/24 (2006.01); H04L 25/03 (2006.01)
CPC (source: EP)
H04L 1/20 (2013.01); H04L 1/241 (2013.01); H04L 1/242 (2013.01); H04L 25/03006 (2013.01)
Citation (search report)
See references of WO 2004105334A2
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2004105334 A2 20041202; WO 2004105334 A3 20050602; EP 1629622 A2 20060301; EP 2148461 A2 20100127
DOCDB simple family (application)
US 2004015895 W 20040520; EP 04752834 A 20040520; EP 09167569 A 20040520