EP 1665104 A2 20060607 - METHOD FOR TESTING AN ELECTRIC CIRCUIT
Title (en)
METHOD FOR TESTING AN ELECTRIC CIRCUIT
Title (de)
VERFAHREN ZUM PRÜFEN EINER ELEKTRISCHEN SCHALTUNG
Title (fr)
PROCEDE DE CONTROLE DE CIRCUIT ELECTRIQUE
Publication
Application
Priority
- DE 2004001951 W 20040831
- DE 10343344 A 20030912
Abstract (en)
[origin: WO2005026994A2] The invention relates to a method for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner. According to the invention, a marking signal is produced, indicating a predefined circuit state which might occur in specific components of an electric circuit, wherein a transformed network list is formed from an original network list describing the circuit, whereby all electric components at least of one predefined component group, with regard to a respective connection pair, are treated as short-circuited, all network nodes connected by one or several components which are to be treated as short-circuited are respectively combined to form an equivalence category, wherein respectively all states of the associated network nodes are assigned to each equivalence category, it is possible to determine whether and in which components the predefined circuit state can occur by taking into account the equivalence categories. A signal which marks the identified components in the original network list is produced as the marking signal.
IPC 1-7
IPC 8 full level
G06F 17/50 (2006.01)
CPC (source: EP US)
G06F 30/327 (2020.01 - EP US); G06F 30/33 (2020.01 - EP US); G06F 30/3308 (2020.01 - US)
Citation (search report)
See references of WO 2005026994A2
Citation (examination)
- US 6591402 B1 20030708 - CHANDRA RAJIT [US], et al
- US 6499129 B1 20021224 - SRINIVASAN ARVIND [US], et al
- US 6389578 B1 20020514 - MCBRIDE JOHN G [US]
- US 6117179 A 20000912 - TAN ALEXIUS H [US], et al
- US 6055366 A 20000425 - LE BINH QUANG [US], et al
- US 2003208721 A1 20031106 - REGNIER JOHN W [US]
- PELZ G ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "An interpreter for general netlist design rule checking", PROCEEDINGS OF THE ACM/IEEE DESIGN AUTOMATION CONFERENCE. ANAHEIM, JUNE 8 - 12, 1992; [PROCEEDINGS OF THE ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC)], LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. CONF. 29, 8 June 1992 (1992-06-08), pages 305 - 310, XP010028934, ISBN: 978-0-8186-2822-1, DOI: 10.1109/DAC.1992.227788
- BHAVSAR D K: "Design for Test Calculus: An Algorithm for DFT Rules Checking", DESIGN AUTOMATION, 1983. 20TH CONFERENCE ON MIAMI BEACH, FL, USA 27-29 JUNE 1983, PISCATAWAY, NJ, USA,IEEE, 27 June 1983 (1983-06-27), pages 300 - 307, XP010888824, ISBN: 978-0-8186-0026-5
Designated contracting state (EPC)
DE FR GB IE IT
DOCDB simple family (publication)
WO 2005026994 A2 20050324; WO 2005026994 A3 20050901; CN 100458798 C 20090204; CN 1849609 A 20061018; DE 10343344 A1 20050504; DE 10343344 B4 20060420; EP 1665104 A2 20060607; JP 2007505295 A 20070308; US 2006230372 A1 20061012; US 7636903 B2 20091222
DOCDB simple family (application)
DE 2004001951 W 20040831; CN 200480026414 A 20040831; DE 10343344 A 20030912; EP 04762738 A 20040831; JP 2006525617 A 20040831; US 37275406 A 20060310