EP 1665105 A2 20060607 - METHOD FOR TESTING AN ELECTRICAL CIRCUIT
Title (en)
METHOD FOR TESTING AN ELECTRICAL CIRCUIT
Title (de)
VERFAHREN ZUM PRÜFEN EINER ELEKTRISCHEN SCHALTUNG
Title (fr)
PROCEDE POUR VERIFIER UN CIRCUIT ELECTRIQUE
Publication
Application
Priority
- DE 2004002011 W 20040907
- DE 10343346 A 20030912
Abstract (en)
[origin: WO2005026995A2] The aim of the invention is to create a method for testing an electrical circuit, which does not require a thorough electrical circuit simulation while reliably identifying circuit faults. Said aim is achieved by a method for generating a fault signal that indicates that a given state of the circuit, which is defined by an electrical state variable, could occur in an electrical circuit. According to the inventive method, all electrical components of the electrical circuit are individually treated as short-circuited or non-conducting regarding each pair of connections of the component, an electrical state variable is permanently allocated to at least one network node or a connecting pin of the electrical circuit, all electrical state variables of the network nodes and connecting pins to which the respective network node or the respective connecting pin is connected via the pairs of connections of the components that are to be treated as short-circuited are allocated to each network node and each connecting pin with the exception of the network nodes and connecting pins having a permanently allocated electrical state variable, and an assessment is made at least based on the allocated state variables as to whether the given circuit state can occur.
IPC 1-7
IPC 8 full level
G06F 17/50 (2006.01)
CPC (source: EP US)
G06F 30/33 (2020.01 - EP US)
Citation (search report)
See references of WO 2005026995A2
Citation (examination)
- US 6055366 A 20000425 - LE BINH QUANG [US], et al
- US 2003208721 A1 20031106 - REGNIER JOHN W [US]
- US 6389578 B1 20020514 - MCBRIDE JOHN G [US]
- US 6117179 A 20000912 - TAN ALEXIUS H [US], et al
- US 6591402 B1 20030708 - CHANDRA RAJIT [US], et al
- US 6499129 B1 20021224 - SRINIVASAN ARVIND [US], et al
- US 7240316 B2 20070703 - REGNIER JOHN W [US]
- BHAVSAR D K: "Design for Test Calculus: An Algorithm for DFT Rules Checking", DESIGN AUTOMATION, 1983. 20TH CONFERENCE ON MIAMI BEACH, FL, USA 27-29 JUNE 1983, PISCATAWAY, NJ, USA,IEEE, 27 June 1983 (1983-06-27), pages 300 - 307, XP010888824, ISBN: 978-0-8186-0026-5
- PELZ G ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "An interpreter for general netlist design rule checking", 8 June 1992, PROCEEDINGS OF THE ACM/IEEE DESIGN AUTOMATION CONFERENCE. ANAHEIM, JUNE 8 - 12, 1992; [PROCEEDINGS OF THE ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC)], LOS ALAMITOS, IEEE COMP. SOC. PRESS, US LNKD- DOI:10.1109/DAC.1992.227788, PAGE(S) 305 - 310, ISBN: 978-0-8186-2822-1, XP010028934
Designated contracting state (EPC)
DE FR GB IE IT
DOCDB simple family (publication)
WO 2005026995 A2 20050324; WO 2005026995 A3 20050901; CN 100429663 C 20081029; CN 1849606 A 20061018; DE 10343346 A1 20050428; DE 10343346 B4 20110127; EP 1665105 A2 20060607; JP 2007505296 A 20070308; US 2006212236 A1 20060921; US 7313498 B2 20071225
DOCDB simple family (application)
DE 2004002011 W 20040907; CN 200480026016 A 20040907; DE 10343346 A 20030912; EP 04786733 A 20040907; JP 2006525619 A 20040907; US 37247006 A 20060309