EP 1735827 A1 20061227 - CREATION OF DIELECTRICALLY INSULATING SOI-TECHNOLOGICAL TRENCHES COMPRISING ROUNDED EDGES FOR ALLOWING HIGHER VOLTAGES
Title (en)
CREATION OF DIELECTRICALLY INSULATING SOI-TECHNOLOGICAL TRENCHES COMPRISING ROUNDED EDGES FOR ALLOWING HIGHER VOLTAGES
Title (de)
ERZEUGUNG VON DIELEKTRISCH ISOLIERENDEN GRAEBEN DER SOI-TECHNOLOGIE MIT ABGERUNDETEN KANTEN FUER HOEHERE SPANNUNGEN
Title (fr)
PRODUCTION DE TRANCHEES A EFFET ISOLANT DIELECTRIQUE RELEVANT DE LA TECHNOLOGIE DE SILICIUM SUR ISOLANT, AVEC DES ARETES ARRONDIES POUR DES TENSIONS SUPERIEURES
Publication
Application
Priority
- DE 2005000618 W 20050407
- DE 102004017073 A 20040407
Abstract (en)
[origin: WO2005098936A1] The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically insulating chip regions having different potentials from each other with the aid of isolating trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolating trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.
IPC 8 full level
H01L 21/762 (2006.01)
CPC (source: EP US)
H01L 21/76235 (2013.01 - EP US)
Citation (search report)
See references of WO 2005098936A1
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2005098936 A1 20051020; DE 102004017073 A1 20051027; DE 102004017073 B4 20120419; EP 1735827 A1 20061227; US 2008265364 A1 20081030; US 7989308 B2 20110802
DOCDB simple family (application)
DE 2005000618 W 20050407; DE 102004017073 A 20040407; EP 05732412 A 20050407; US 59972605 A 20050407