EP 1784021 A3 20071226 - Video processing with multiple graphics processing units
Title (en)
Video processing with multiple graphics processing units
Title (de)
Videobearbeitung mit mehrfachen Grafikbearbeitungseinheiten
Title (fr)
Traitement de vidéo avec plusieurs unitées de traitement graphique
Publication
Application
Priority
US 26761105 A 20051104
Abstract (en)
[origin: EP1784021A2] One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.
IPC 8 full level
H04N 7/26 (2006.01); G06F 12/00 (2006.01); H04N 5/44 (2006.01)
CPC (source: EP KR US)
G06F 3/14 (2013.01 - EP US); G06T 1/20 (2013.01 - EP US); G06T 1/60 (2013.01 - KR); G09G 5/363 (2013.01 - EP US); H04N 7/012 (2013.01 - EP US); G09G 5/399 (2013.01 - EP US); G09G 2360/06 (2013.01 - EP US)
Citation (search report)
- [XA] EP 0584982 A2 19940302 - IBM [US]
- [XA] US 6359624 B1 20020319 - KUNIMATSU ATSUSHI [JP]
- [A] US 6624816 B1 20030923 - JONES JR MORRIS E [US]
- [A] EP 0627700 A2 19941207 - SUN MICROSYSTEMS INC [US]
- [A] JAMES D V ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "Scalable I/O architecture for buses", INTELLECTUAL LEVERAGE. SAN FRANCISCO, FEB. 27 - MAR. 3, 1989, COMPUTER SOCIETY INTERNATIONAL CONFERENCE (COMPCON), WASHINGTON, IEEE COMP. SOC. PRESS, US, vol. CONF. 34, 27 February 1989 (1989-02-27), pages 539 - 544, XP010014807, ISBN: 0-8186-1909-0
- [A] MARIE-JEAN COLAITIS ET AL: "The Implementation of <maths><tex>${\bf{P}}<3>{\bf{I}}$</tex></maths>, a Parallel Architecture for Video Real-Time Processing: A Case Study", PROCEEDINGS OF THE IEEE, IEEE. NEW YORK, US, vol. 84, no. 7, July 1996 (1996-07-01), XP011043720, ISSN: 0018-9219
- [A] SCHOMBERG H ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "A transputer-based shuffle-shift machine for image processing and reconstruction", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PATTERN RECOGNITION. ATLANTIC CITY, JUNE 16 - 21, 1990. CONFERENCE A : COMPUTER VISION AND CONFERENCE B : PATTERN RECOGNITION SYSTEMS AND APPLICATIONS, LOS ALAMITOS, IEEE COMP. SOC. PRESS, US, vol. VOL. 1 CONF. 10, 16 June 1990 (1990-06-16), pages 445 - 450, XP010020432, ISBN: 0-8186-2062-5
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
Designated extension state (EPC)
AL BA HR MK YU
DOCDB simple family (publication)
EP 1784021 A2 20070509; EP 1784021 A3 20071226; EP 1784021 B1 20100519; CA 2567079 A1 20070504; CN 104767956 A 20150708; CN 1960438 A 20070509; DE 602006014344 D1 20100701; JP 2007215156 A 20070823; JP 4568711 B2 20101027; KR 100830286 B1 20080519; KR 20070048634 A 20070509; TW 200731076 A 20070816; TW I339795 B 20110401; US 2007103590 A1 20070510; US 2009207178 A1 20090820; US 7525548 B2 20090428; US 7821517 B2 20101026
DOCDB simple family (application)
EP 06022906 A 20061103; CA 2567079 A 20061103; CN 200610152887 A 20061106; CN 201510095459 A 20061106; DE 602006014344 T 20061103; JP 2006300740 A 20061106; KR 20060109042 A 20061106; TW 95140893 A 20061103; US 26761105 A 20051104; US 43079709 A 20090427