Global Patent Index - EP 1797665 A4

EP 1797665 A4 20100526 - A METHOD AND APPARATUS FOR ENSURING HIGH QUALITY AUDIO PLAYBACK IN A WIRELESS OR WIRED DIGITAL AUDIO COMMUNICATION SYSTEM

Title (en)

A METHOD AND APPARATUS FOR ENSURING HIGH QUALITY AUDIO PLAYBACK IN A WIRELESS OR WIRED DIGITAL AUDIO COMMUNICATION SYSTEM

Title (de)

VERFAHREN UND VORRICHTUNG ZUR SICHERSTELLUNG VON QUALITATIV HOCHWERTIGER AUDIO-WIEDERGABE IN EINEM DRAHTLOSEN ODER VERDRAHTETEN DIGITALEN AUDIO-KOMMUNIKATIONSSYSTEM

Title (fr)

PROCEDE ET APPAREIL PERMETTANT DE GARANTIR UNE LECTURE AUDIO DE HAUTE QUALITE DANS UN SYSTEME DE COMMUNICATION AUDIO NUMERIQUE AVEC OU SANS FIL

Publication

EP 1797665 A4 20100526 (EN)

Application

EP 05788784 A 20050921

Priority

  • IB 2005002783 W 20050921
  • US 61200704 P 20040922

Abstract (en)

[origin: WO2006032978A2] A communication system synchronizes data received and recovered from a transmission medium to the data transmitted such the there is neither under-run nor overrun of the data due to differences in the transmission and reception timing. The data communication system has a transmitter and a receiver. The transmitter encodes digital data into series of symbols and transmits a modulated signal composed of the series of symbols. The receiver acquires the modulated signal, restoring the modulated signal, reconstructing the symbols of the digital data from the modulated signal and synchronizing the digital data to a first reference signal. The digital data is transferred to a buffer data retention circuit. The digital data is transferred from the buffer retention circuit to a jitter management unit. A boundary marker signal detection circuit extracts a marker signal indicating a boundary of symbols of the digital data to provide an indication of the timing of the digital data as broadcasted by the transmitter. A jitter management unit synchronizes the digital data to the first reference signal. The jitter management unit has a FIFO buffer to receive the reconstructed digital data at the rate of the first reference signal from the buffer retention circuit and transmits the synchronized digital data at a rate approximating the timing of the transmitter. The jitter management unit synchronizes the digital data by monitoring the level of the digital data present within the FIFO buffer and adjusting the consumption of the digital data from the FIFO buffer.

IPC 8 full level

H04J 3/06 (2006.01); H04L 1/00 (2006.01); H04L 1/20 (2006.01); H04L 7/033 (2006.01); H04L 7/08 (2006.01)

CPC (source: EP KR)

H04J 3/0632 (2013.01 - EP); H04L 1/00 (2013.01 - KR); H04L 1/20 (2013.01 - KR); H04L 7/033 (2013.01 - KR); H04R 1/1041 (2013.01 - EP); H04R 1/1008 (2013.01 - EP); H04R 2420/07 (2013.01 - EP)

Citation (search report)

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

DOCDB simple family (publication)

WO 2006032978 A2 20060330; WO 2006032978 A3 20061228; EP 1797665 A2 20070620; EP 1797665 A4 20100526; JP 2008514148 A 20080501; KR 20070085235 A 20070827; TW 200625903 A 20060716; TW I304694 B 20081221

DOCDB simple family (application)

IB 2005002783 W 20050921; EP 05788784 A 20050921; JP 2007532980 A 20050921; KR 20077006722 A 20070323; TW 94132495 A 20050920