Title (en)

INTEGRATED CIRCUIT WITH PHASE-CHANGE MEMORY CELLS AND METHOD FOR ADDRESSING PHASE-CHANGE MEMORY CELLS

Title (de)

INTEGRIERTE SCHALTUNG MIT PHASENÄNDERUNGS-SPEICHERZELLEN UND VERFAHREN ZUM ADRESSIEREN VON PHASENÄNDERUNGS-SPEICHERZELLEN

Title (fr)

CIRCUIT INTEGRE DOTE DE CELLULES DE MEMOIRE A CHANGEMENT DE PHASE ET PROCEDE D'ADRESSAGE DE CELLULES DE MEMOIRE A CHANGEMENT DE PHASE

Publication

EP 1807840 A1 20070718 (EN)

Application

EP 05792269 A 20051017

Priority

• IB 2005053399 W 20051017
• EP 04105212 A 20041021
• EP 05792269 A 20051017

Abstract (en)

[origin: WO2006043230A1] The present invention relates to integrated circuit comprising a plurality of bit­lines (bl) and a plurality of word-lines (wl) as well as a plurality of memory-cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (bl) and word­lines (wl) for storing data in the memory cell. Each memory cell (MC) comprises a selecting unit (T) and a programmable resistance (R). The value of the phase-change resistance (R) is greater than the value of a first phase-change resistance (R<sub

IPC 8 full level

G11C 16/02 (2006.01)

CPC (source: EP KR US)

G11C 13/0004 (2013.01 - EP US); G11C 13/02 (2013.01 - KR)

Citation (search report)

See references of WO 2006043230A1

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

DOCDB simple family (publication)

WO 2006043230 A1 20060427; AT E469419 T1 20100615; CN 101044577 A 20070926; CN 101044577 B 20110615; DE 602005021527 D1 20100708; EP 1807840 A1 20070718; EP 1807840 B1 20100526; JP 2008518373 A 20080529; KR 20070067150 A 20070627; TW 200627457 A 20060801; US 2009067226 A1 20090312; US 7911822 B2 20110322

DOCDB simple family (application)

IB 2005053399 W 20051017; AT 05792269 T 20051017; CN 200580036076 A 20051017; DE 602005021527 T 20051017; EP 05792269 A 20051017; JP 2007537444 A 20051017; KR 20077008869 A 20070419; TW 94136426 A 20051018; US 57770805 A 20051017