Global Patent Index - EP 1844381 A4

EP 1844381 A4 2009-02-25 - STANDARD CMOS LOW-NOISE HIGH PSRR LOW DROP-OUT REGULATOR WITH NEW DYNAMIC COMPENSATION

Title (en)

STANDARD CMOS LOW-NOISE HIGH PSRR LOW DROP-OUT REGULATOR WITH NEW DYNAMIC COMPENSATION

Title (de)

RAUSCHARMER STANDARD-CMOS-REGLER MIT GERINGER ABFALLSPANNUNG, HOHER PSRR UND NEUER DYNAMISCHER KOMPENSATION

Title (fr)

REGULATEUR A FAIBLE DESEXCITATION, A PSRR ELEVE, A FAIBLE BRUIT, CMOS STANDARD AVEC COMPENSATION DYNAMIQUE NOUVELLE

Publication

EP 1844381 A4 (EN)

Application

EP 06717728 A

Priority

  • US 2006000563 W
  • FR 0500890 A
  • US 11913005 A

Abstract (en)

[origin: WO2006083490A2] A voltage regulator circuit (200) has a first amplifier stage (210) with input and output terminals, a feedback terminal, a pole-inducing transistor, and a compensating network coupled to the output terminal. A second amplifier stage (220) has an input coupled to the first amplifier output, first and second current mirrors, and a pass transistor.

IPC 8 full level (invention and additional information)

G05F 1/40 (2006.01); G05F 1/44 (2006.01); G05F 1/56 (2006.01); G05F 1/565 (2006.01); G05F 1/618 (2006.01)

CPC (invention and additional information)

G05F 1/565 (2013.01); G05F 1/575 (2013.01)

Citation (search report)

Designated contracting state (EPC)

DE GB

DOCDB simple family

WO 2006083490 A2 20060810; WO 2006083490 A3 20080320; EP 1844381 A2 20071017; EP 1844381 A4 20090225