EP 1905084 A2 20080402 - INTEGRATED CIRCUIT WITH ELECTRO-STATIC DISCHARGE PROTECTION
Title (en)
INTEGRATED CIRCUIT WITH ELECTRO-STATIC DISCHARGE PROTECTION
Title (de)
INTEGRIERTE SCHALTUNG MIT SCHUTZ VOR ELEKTROSTATISCHEN ENTLADUNGEN
Title (fr)
CIRCUIT INTEGRE DOTE D'UNE PROTECTION CONTRE DES DECHARGES ELECTROSTATIQUES
Publication
Application
Priority
- IB 2006052252 W 20060704
- EP 05106282 A 20050708
- EP 06766003 A 20060704
Abstract (en)
[origin: WO2007007237A2] A rail-based Electro- Static Discharge (ESD) protection scheme for multi- voltage-domain Integrated Circuits (ICs) is proposed. Distributed parts of clamp transistors (Tl, T2) for every voltage domain are comprised within each I/O cell (LV IO, HV IO), no matter to which voltage domain it belongs. These clamp transistors are activated using a dedicated power track for each voltage domain. An ESD trigger circuit (TCl, TC2) senses first and second supply voltages and sends signals via respective power tracks to respective first and second clamp devices inside all I/O cells in case an ESD event is detected. The ESD protection scheme according to the invention provides the flexibility in placing circuits and I/O cells on a die of the IC, since it does not matter which voltage domain these I/O cells refer to. The invention is suitable for ICs with considerable difference in supply voltages, e.g. 3 V and 20V.
IPC 8 full level
H01L 27/02 (2006.01)
CPC (source: EP)
H01L 27/0251 (2013.01); H01L 27/0292 (2013.01)
Citation (search report)
See references of WO 2007007237A2
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2007007237 A2 20070118; WO 2007007237 A3 20070329; CN 101258597 A 20080903; EP 1905084 A2 20080402; JP 2009500840 A 20090108
DOCDB simple family (application)
IB 2006052252 W 20060704; CN 200680032723 A 20060704; EP 06766003 A 20060704; JP 2008520044 A 20060704