EP 1925084 A4 20081126 - INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT
Title (en)
INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT
Title (de)
INTEGRIERTE SCHALTUNGEN MIT VERRINGERTEM LECKSTROM
Title (fr)
CIRCUITS INTEGRES A COURANT DE FUITE REDUIT
Publication
Application
Priority
- US 2006032551 W 20060816
- US 70872905 P 20050816
- US 30123605 A 20051212
Abstract (en)
[origin: US2007040575A1] In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.
IPC 8 full level
H03K 19/003 (2006.01)
CPC (source: EP US)
H03K 19/0016 (2013.01 - EP US)
Citation (search report)
- [X] WO 0067380 A1 20001109 - INTEL CORP [US], et al
- [X] US 2005146948 A1 20050707 - HOSE RICHARD K JR [US], et al
- [X] US 2002158665 A1 20021031 - YE YIBIN [US], et al
- See references of WO 2007022491A2
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
US 2007040575 A1 20070222; US 7271615 B2 20070918; EP 1925084 A2 20080528; EP 1925084 A4 20081126; JP 2009505588 A 20090205; US 2008224729 A1 20080918; WO 2007022491 A2 20070222; WO 2007022491 A3 20071129
DOCDB simple family (application)
US 30123605 A 20051212; EP 06789891 A 20060816; JP 2008527203 A 20060816; US 2006032551 W 20060816; US 85713307 A 20070918