EP 1966889 B1 20111102 - ELECTRONIC CIRCUIT WITH LOW NOISE DELAY CIRCUIT
Title (en)
ELECTRONIC CIRCUIT WITH LOW NOISE DELAY CIRCUIT
Title (de)
ELEKTRONISCHE SCHALTUNG MIT RAUSCHARMER VERZÖGERUNGSSCHALTUNG
Title (fr)
CIRCUIT ELECTRONIQUE INCORPORANT UN CIRCUIT A RETARD A FAIBLE BRUIT
Publication
Application
Priority
- IB 2006054784 W 20061212
- EP 05112458 A 20051220
- EP 06842462 A 20061212
Abstract (en)
[origin: WO2007072307A1] An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (10a-d), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit (104) and a current modulator (106) coupled to the integrating circuit (104). Each stage triggers a transition in the next stage when the integration result reaches a level defined by a reference voltage. Correlating circuitry (102, 30, 32, 34) is provided with current outputs to generate currents to the current modulators (106) and reference voltages for the saw tooth delay stages (10a-d). The reference voltages are generated at least partly from a common reference (102c), so that noise in the currents from the current modulators (106) and reference voltages is correlated in a way that at least partly cancels the effect of the noise on the delay time.
IPC 8 full level
CPC (source: EP US)
H03K 3/354 (2013.01 - EP US); H03K 4/502 (2013.01 - EP US)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2007072307 A1 20070628; AT E532262 T1 20111115; CN 101341655 A 20090107; CN 101341655 B 20120704; EP 1966889 A1 20080910; EP 1966889 B1 20111102; JP 2009520426 A 20090521; JP 4961525 B2 20120627; US 2009051399 A1 20090226; US 7570097 B2 20090804
DOCDB simple family (application)
IB 2006054784 W 20061212; AT 06842462 T 20061212; CN 200680047943 A 20061212; EP 06842462 A 20061212; JP 2008546728 A 20061212; US 15831506 A 20061212