EP 1989711 A4 20090805 - METHOD AND APPARATUS FOR CASCADE MEMORY
Title (en)
METHOD AND APPARATUS FOR CASCADE MEMORY
Title (de)
VERFAHREN UND VORRICHTUNG FÜR KASKADENSPEICHER
Title (fr)
PROCÉDÉ ET DISPOSITIF POUR MÉMOIRE EN CASCADE
Publication
Application
Priority
- SG 2006000235 W 20060817
- SG 2006012512 A 20060227
Abstract (en)
[origin: WO2007097712A1] A memory device having a memory cell and a memory controller operatively connected to the memory cell. A cascade circuit is provided for enabling a subsequent memory device in a cascade of memory devices. The cascade circuit is operatively connected to the memory controller. A corresponding method is also disclosed.
IPC 8 full level
CPC (source: EP KR US)
G06F 7/00 (2013.01 - KR); G06F 13/00 (2013.01 - KR); G11C 5/04 (2013.01 - EP US); G11C 7/10 (2013.01 - KR)
Citation (search report)
- [X] WO 9632724 A1 19961017 - CIRRUS LOGIC INC [US]
- [X] JP S6379290 A 19880409 - HITACHI VLSI ENG, et al
- See references of WO 2007097712A1
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2007097712 A1 20070830; BR PI0621373 A2 20111206; CN 101375339 A 20090225; CN 101375339 B 20120530; EP 1989711 A1 20081112; EP 1989711 A4 20090805; JP 2009528588 A 20090806; JP 5037535 B2 20120926; KR 101270179 B1 20130531; KR 20080105055 A 20081203; RU 2008134388 A 20100410; SG 135073 A1 20070928; US 2009070522 A1 20090312; US 8443132 B2 20130514
DOCDB simple family (application)
SG 2006000235 W 20060817; BR PI0621373 A 20060817; CN 200680052854 A 20060817; EP 06784254 A 20060817; JP 2008556282 A 20060817; KR 20087021510 A 20080902; RU 2008134388 A 20060817; SG 2006012512 A 20060227; US 18961008 A 20080811