EP 2050241 A1 20090422 - CHIP EQUALIZER AND EQUALIZING METHOD
Title (en)
CHIP EQUALIZER AND EQUALIZING METHOD
Title (de)
CHIP-ENTZERRER UND ENTZERRUNGSVERFAHREN
Title (fr)
ÉGALISEUR AU NIVEAU CHIP ET PROCÉDÉ D'ÉGALISATION
Publication
Application
Priority
- KR 2007003788 W 20070807
- KR 20060074288 A 20060807
Abstract (en)
[origin: WO2008018736A1] Disclosed are a chip equalizer and an equalizing method capable of minimizing complexity for signal demodulation in accordance with performance of a receiver. The chip equalizer comprises a delay control module that recognizes an area having a main signal included therein from a signal distribution of signals received from a tuner and determines a noise compensation area in accordance with a delay difference between neighboring main signals; at least one first unit delay module that delays, among the signals received from the tuner, a signal of the area having the main signal included therein at an interval of a chip unit and outputs it to a tap co¬ efficient estimation module; and at least one second module that delays, among the signals received from the tuner, a signal of an area having no main signal included therein at an interval of a chip unit.
IPC 8 full level
H04L 27/01 (2006.01)
CPC (source: EP KR)
H04B 7/005 (2013.01 - KR); H04L 25/03038 (2013.01 - EP); H04L 27/01 (2013.01 - KR); H04L 1/0045 (2013.01 - EP); H04L 1/0065 (2013.01 - EP)
Designated contracting state (EPC)
FR
Designated extension state (EPC)
AL BA HR MK RS
DOCDB simple family (publication)
WO 2008018736 A1 20080214; CN 101502068 A 20090805; CN 101502068 B 20120530; EP 2050241 A1 20090422; EP 2050241 A4 20170913; KR 101393428 B1 20140627; KR 20090038001 A 20090417
DOCDB simple family (application)
KR 2007003788 W 20070807; CN 200780029346 A 20070807; EP 07793400 A 20070807; KR 20097000187 A 20070807