EP 2054803 A2 20090506 - MEMORY CIRCUIT SYSTEM AND METHOD
Title (en)
MEMORY CIRCUIT SYSTEM AND METHOD
Title (de)
SPEICHERSCHALTUNGSSYSTEM UND -VERFAHREN
Title (fr)
SYSTÈME ET PROCÉDÉ DE CIRCUIT DE MÉMOIRE
Publication
Application
Priority
- US 2007016385 W 20070718
- US 46143906 A 20060731
- US 52481106 A 20060920
- US 52473006 A 20060920
- US 52481206 A 20060920
- US 52471606 A 20060920
- US 53804106 A 20061002
- US 58417906 A 20061020
- US 76201007 A 20070612
- US 76201307 A 20070612
Abstract (en)
[origin: WO2008063251A2] A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
IPC 8 full level
G06F 1/00 (2006.01); G06F 9/455 (2006.01); G06F 12/00 (2006.01)
CPC (source: EP)
G06F 1/3225 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 5/148 (2013.01); G11C 11/4074 (2013.01); G06F 2213/0038 (2013.01); G11C 8/12 (2013.01); G11C 11/40611 (2013.01); G11C 2207/2272 (2013.01); G11C 2211/4067 (2013.01)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR
Designated extension state (EPC)
AL BA HR MK RS
DOCDB simple family (publication)
WO 2008063251 A2 20080529; WO 2008063251 A3 20081016; DK 3364298 T3 20200302; EP 2054803 A2 20090506; EP 2054803 A4 20091021; EP 2442309 A2 20120418; EP 2442309 A3 20130123; EP 2442310 A2 20120418; EP 2442310 A3 20130424; EP 3364298 A2 20180822; EP 3364298 A3 20181128; EP 3364298 B1 20191211
DOCDB simple family (application)
US 2007016385 W 20070718; DK 18166674 T 20070718; EP 07870726 A 20070718; EP 12150798 A 20070718; EP 12150807 A 20070718; EP 18166674 A 20070718