EP 2097800 A1 20090909 - SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL
Title (en)
SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL
Title (de)
GESCHWINDIGKEITS-BINNING FÜR DYNAMISCHE UND ADAPTIVE LEISTUNGSREGELUNG
Title (fr)
SÉLECTION DE VITESSE POUR COMMANDE DE PUISSANCE DYNAMIQUE ET ADAPTATIVE
Publication
Application
Priority
US 2006061323 W 20061129
Abstract (en)
[origin: WO2008066548A1] A representative digital circuit of the invention has an on-chip, non- volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit.
IPC 8 full level
G06F 1/32 (2006.01)
CPC (source: EP KR US)
G01R 31/00 (2013.01 - KR); G06F 1/26 (2013.01 - KR); G06F 1/32 (2013.01 - KR); G06F 1/3203 (2013.01 - EP US); G06F 11/22 (2013.01 - KR)
Citation (search report)
See references of WO 2008066548A1
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2008066548 A1 20080605; EP 2097800 A1 20090909; JP 2010511247 A 20100408; JP 5524623 B2 20140618; KR 20090087021 A 20090814; US 2010017042 A1 20100121; US 8234511 B2 20120731
DOCDB simple family (application)
US 2006061323 W 20061129; EP 06840051 A 20061129; JP 2009539228 A 20061129; KR 20097011052 A 20061129; US 44688109 A 20090423