EP 2097924 A2 20090909 - FRONT-END PROCESSED WAFER HAVING THROUGH-CHIP CONNECTIONS
Title (en)
FRONT-END PROCESSED WAFER HAVING THROUGH-CHIP CONNECTIONS
Title (de)
FRONT-END-VERARBEITETER WAFER MIT VERBINDUNGEN DURCH CHIP
Title (fr)
TRANCHE TRAITÉE AU NIVEAU DE L'EXTRÉMITÉ FRONTALE AYANT DES CONNEXIONS TRAVERSANT LES PUCES
Publication
Application
Priority
- US 2007089061 W 20071228
- US 88267106 P 20061229
Abstract (en)
[origin: WO2008083284A2] A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metalization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.
IPC 8 full level
H01L 21/768 (2006.01); H01L 23/48 (2006.01)
CPC (source: EP KR)
H01L 21/768 (2013.01 - KR); H01L 21/76898 (2013.01 - EP); H01L 23/481 (2013.01 - EP); H01L 2924/0002 (2013.01 - EP)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2008083284 A2 20080710; WO 2008083284 A3 20080821; CN 101663742 A 20100303; CN 101663742 B 20131106; EP 2097924 A2 20090909; EP 2097924 A4 20120104; JP 2010515275 A 20100506; JP 2013175786 A 20130905; JP 5686851 B2 20150318; KR 101088926 B1 20111201; KR 20090094371 A 20090904
DOCDB simple family (application)
US 2007089061 W 20071228; CN 200780047912 A 20071228; EP 07870039 A 20071228; JP 2009544291 A 20071228; JP 2013115456 A 20130531; KR 20097014823 A 20071228