EP 2107746 A3 20091230 - High speed signaling system with adaptive transmit pre-emphasis, reflection cancellation and offset cancellation
Title (en)
High speed signaling system with adaptive transmit pre-emphasis, reflection cancellation and offset cancellation
Title (de)
Schnelles Signalisierungssystem mit adaptiver Vorverzerrung, Auslöschung von Reflexionen und Unterdrückung von Gleichspannungsversätzen
Title (fr)
Systeme de signalisation à vitesse elevée à preaccentuation, annulation de réflexion et annulation de décalage du niveau continu adaptives
Publication
Application
Priority
- EP 04814386 A 20041216
- US 74008703 A 20031217
- US 85150504 A 20040521
- US 87508604 A 20040623
Abstract (en)
[origin: US2005134305A1] A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling circuit samples the first signal to determine whether the first signal exceeds a second threshold. The drive strength of the output driver circuit is adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds, and the second threshold is adjusted based, at least in part, on whether the first signal exceeds the second threshold.
IPC 8 full level
H03K 19/003 (2006.01); H04L 25/02 (2006.01); H04L 25/03 (2006.01); H04L 25/06 (2006.01); H04L 25/49 (2006.01)
CPC (source: EP US)
H04B 1/04 (2013.01 - US); H04B 1/0475 (2013.01 - US); H04L 25/025 (2013.01 - US); H04L 25/028 (2013.01 - EP US); H04L 25/03019 (2013.01 - US); H04L 25/03343 (2013.01 - EP US); H04L 25/03885 (2013.01 - EP US); H04L 25/061 (2013.01 - EP US); H04L 25/49 (2013.01 - US); H04L 25/4917 (2013.01 - EP US); H04B 2001/0416 (2013.01 - US); H04L 25/0282 (2013.01 - EP US); H04L 2025/03363 (2013.01 - EP US); H04L 2025/03802 (2013.01 - EP US)
Citation (search report)
- [X] US 5254883 A 19931019 - HOROWITZ MARK A [US], et al
- [A] US 2002057101 A1 20020516 - TANG BENJAMIM [US], et al
- [A] US 6377076 B1 20020423 - GAUTHIER CLAUDE R [US]
- [A] CHEN F ET AL: "Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 38, no. 12, 1 December 2003 (2003-12-01), pages 2121 - 2130, XP011104331, ISSN: 0018-9200
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
US 2005134305 A1 20050623; US 7126378 B2 20061024; EP 2107746 A2 20091007; EP 2107746 A3 20091230; EP 2107746 B1 20160928; US 10411923 B2 20190910; US 10771295 B2 20200908; US 11233678 B2 20220125; US 11706061 B2 20230718; US 2005134306 A1 20050623; US 2006158225 A1 20060720; US 2007080718 A1 20070412; US 2009002030 A1 20090101; US 2010117706 A1 20100513; US 2012288027 A1 20121115; US 2013272359 A1 20131017; US 2013272446 A1 20131017; US 2015222303 A1 20150806; US 2016218895 A1 20160728; US 2017338981 A1 20171123; US 2020084073 A1 20200312; US 2021051047 A1 20210218; US 2022209999 A1 20220630; US 7030657 B2 20060418; US 7199615 B2 20070403; US 7423454 B2 20080909; US 7656981 B2 20100202; US 8183887 B2 20120522; US 8564328 B2 20131022; US 8994398 B2 20150331; US 9000803 B2 20150407; US 9287909 B2 20160315; US 9705710 B2 20170711
DOCDB simple family (application)
US 74008703 A 20031217; EP 09165754 A 20041216; US 201213476247 A 20120521; US 201313913156 A 20130607; US 201313913242 A 20130607; US 201514620163 A 20150211; US 201615006041 A 20160125; US 201715616408 A 20170607; US 201916548708 A 20190822; US 202017000191 A 20200821; US 202217573471 A 20220111; US 20662908 A 20080908; US 38698406 A 20060321; US 53833306 A 20061003; US 69328510 A 20100125; US 85150504 A 20040521