EP 2109890 A4 20100210 - DEPLETION-MODE MOSFET CIRCUIT AND APPLICATIONS
Title (en)
DEPLETION-MODE MOSFET CIRCUIT AND APPLICATIONS
Title (de)
MOSFET-SCHALTUNG MIT VERARMUNGSSCHICHT UND ANWENDUNGEN
Title (fr)
CIRCUIT MOSFET A MODE D'APPAUVRISSEMENT ET APPLICATIONS
Publication
Application
Priority
- US 2008051913 W 20080124
- US 88636307 P 20070124
Abstract (en)
[origin: WO2008092004A2] Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.
IPC 8 full level
H01L 27/088 (2006.01); G11C 11/412 (2006.01)
CPC (source: EP)
H01L 27/0255 (2013.01); H01L 27/0266 (2013.01)
Citation (search report)
- [XY] US 5966324 A 19991012 - WADA TOMOHISA [JP], et al
- [XY] US 4062000 A 19771206 - DONNELLY ROBERT MURRAY
- See references of WO 2008092004A2
Citation (examination)
- US 6363005 B1 20020326 - WANG CHENG-LIEH [TW], et al
- US 6992915 B2 20060131 - KANG SUNG-MO [US], et al
- US 6639835 B2 20031028 - FORBES LEONARD [US]
- Y. TAKAHASHI ET AL.: "A Multiple-Valued SRAM with Combined Single-Electron and MOS Transistors", IEEE TRANS.ELECTRON DEVICES, vol. 43, 1996, pages 1213 - 1214, XP002627000
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2008092004 A2 20080731; WO 2008092004 A3 20081016; CN 101632176 A 20100120; EP 2109890 A2 20091021; EP 2109890 A4 20100210; EP 2287908 A2 20110223; EP 2287909 A2 20110223; JP 2010517204 A 20100520
DOCDB simple family (application)
US 2008051913 W 20080124; CN 200880005697 A 20080124; EP 08728213 A 20080124; EP 10172459 A 20080124; EP 10172462 A 20080124; JP 2009547419 A 20080124