Global Patent Index - EP 2171698 A2

EP 2171698 A2 20100407 - ARRANGEMENT IN A MULTILAYER FLOOR COVERING

Title (en)

ARRANGEMENT IN A MULTILAYER FLOOR COVERING

Title (de)

ANORDNUNG VON HALBLEITERCHIPS IN EINEM MEHRLAGIGEN BODENBELAG

Title (fr)

ARRANGEMENT DANS UN REVÊTEMENT DE SOL MULTICOUCHE

Publication

EP 2171698 A2 20100407 (DE)

Application

EP 08774821 A 20080707

Priority

  • EP 2008058747 W 20080707
  • DE 102007031964 A 20070710

Abstract (en)

[origin: WO2009007335A2] The invention relates to an arrangement of chips (10) bonded with sensors (7) in a multilayer floor covering. In order further to improve an arrangement of the type under consideration herein, in a simpler way of technical production, the invention proposes that in a first upper layer (1) circuit paths (4) are formed, separated from each other in a plane, to provide power to a chip (10), that a second middle layer (2) is provided in which the chip (10) is located, and that a third lower layer (3) is provided which likewise is connected electrically to the chip (10), wherein sensors (7) are located in the surface gaps between the chips (10).

IPC 8 full level

G08B 13/10 (2006.01); G01L 1/14 (2006.01); G08B 13/26 (2006.01); H01H 3/14 (2006.01)

CPC (source: EP)

G08B 13/10 (2013.01)

Citation (search report)

See references of WO 2009007335A2

Designated contracting state (EPC)

AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

Designated extension state (EPC)

AL BA MK RS

DOCDB simple family (publication)

DE 102007031964 A1 20090115; EP 2171698 A2 20100407; WO 2009007335 A2 20090115; WO 2009007335 A3 20090409

DOCDB simple family (application)

DE 102007031964 A 20070710; EP 08774821 A 20080707; EP 2008058747 W 20080707