Global Patent Index - EP 2452264 A1

EP 2452264 A1 20120516 - SYSTEM-ON-CHIP FAULT IDENTIFICATION

Title (en)

SYSTEM-ON-CHIP FAULT IDENTIFICATION

Title (de)

SYSTEM-ON-CHIP FEHLERERKENNUNG

Title (fr)

DÉTECTION D'ERREURS POUR SYSTÈME SUR PUCE

Publication

EP 2452264 A1 (DE)

Application

EP 10744654 A

Priority

  • AT 2010000248 W
  • AT 10772009 A

Abstract (en)

[origin: WO2011003121A1] The invention relates to a method for fault identification in a System-on-Chip (SoC) consisting of a number of IP cores, wherein each IP core is a fault containment unit, and where the IP cores communicate with one another by means of messages via a Network-on-Chip, and wherein an excellent IP core provides a TRM (Trusted Resource Monitor), wherein a faulty control message which is sent from one non-privileged IP core to another non-privileged IP core is identified and projected by an (independent) fault container unit, as a result of which this faulty control message cannot cause any failure of the message receiver.

IPC 8 full level

G06F 11/00 (2006.01); G06F 15/78 (2006.01); H04L 12/56 (2006.01)

CPC (source: EP)

G06F 11/004 (2013.01); G06F 11/2736 (2013.01); G06F 15/7825 (2013.01); H04L 49/109 (2013.01); H04L 49/552 (2013.01); H04L 49/555 (2013.01); G06F 11/184 (2013.01)

Citation (search report)

See references of WO 2011003121A1

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

DOCDB simple family (publication)

WO 2011003121 A1 20110113; CN 102473121 A 20120523; EP 2452264 A1 20120516; JP 2012532385 A 20121213; US 2012124411 A1 20120517; US 8732522 B2 20140520

DOCDB simple family (application)

AT 2010000248 W 20100707; CN 201080031112 A 20100707; EP 10744654 A 20100707; JP 2012518691 A 20100707; US 201013383011 A 20100707