Global Patent Index - EP 2627008 A2

EP 2627008 A2 20130814 - Channel codec processor configurable for multiple wireless communications standards

Title (en)

Channel codec processor configurable for multiple wireless communications standards

Title (de)

Für mehrere drahtlose Kommunikationsstandards konfigurierbarer Kanal-Codec-Prozessor

Title (fr)

Processeur CODEC de canal configurable pour des communications sans fil multiples

Publication

EP 2627008 A2 20130814 (EN)

Application

EP 13162380 A 20011228

Priority

  • US 25886500 P 20001229
  • EP 01985596 A 20011228

Abstract (en)

A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and reconfigurability is provided by the channel CODEC processor (200). In particular, the reconfigurable channel CODEC processor includes processor cores (210, 250) and algorithm-specific kernels (212, 214,216, 252, 254, 256) that contain logic circuits tailored for carrying out predetermined but user-configurable decoding and encoding algorithms. The interconnects (230, 270) between the processor cores and the algorithm-specific kernels are also user-configurable. Thus, the same hardware can be reconfigured for many different wireless communication standards.

IPC 8 full level

H03M 13/00 (2006.01); H03M 13/09 (2006.01); H03M 13/23 (2006.01); H03M 13/29 (2006.01); H03M 13/41 (2006.01); H04L 1/00 (2006.01)

CPC (source: EP US)

H03M 13/6511 (2013.01 - EP US); H03M 13/6569 (2013.01 - EP US); H04L 1/0041 (2013.01 - EP US); H04L 1/0045 (2013.01 - EP US); H04L 1/005 (2013.01 - EP US); H04L 1/0066 (2013.01 - EP US); H03M 13/09 (2013.01 - EP US); H03M 13/29 (2013.01 - EP US); H03M 13/2957 (2013.01 - EP US); H03M 13/41 (2013.01 - EP US)

Citation (applicant)

  • US 77258401 A 20010129
  • US 82838101 A 20010405
  • A. VITERBI: "Error bounds for convolutional coding and an asymptotically optimal decoding algorithm", IEEE TRANS. INFORMATION THEORY, vol. IT-13, April 1967 (1967-04-01), pages 260 - 269
  • G. FOMEY: "The Viterbi algorithm", PROC. OF THE IEEE, vol. 61, March 1973 (1973-03-01)
  • S. BITTERTICH; H. DAWID; H. MEYR, PROCEEDINGS IEEE GLOBAL COMMUNICATIONS CONFERENCE GLOBECOM, 1992, pages 1260 - 65
  • S. BITTERLICH; B. PAPE; H. MEYR: "Area Efficient Viterbi-Decoder Macros", PROCEEDINGS OF THE EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)'94
  • M. VAUPEL; U. LAMBRETTE; H. DAWID; O. S. BITTERLICH; H. MEYR; F. FRIELING; K. MUELLER: "Integrated Systems on Silicon", 1997, CHAPMAN HALL, article "An all Digital Single-Chip Symbol Synchronizer and Channel Decoder for DVB", pages: 79 - 90
  • KAI HWANG: "Advanced computer architecture", 1993, MCGRAW-HILL INTERNATIONAL
  • H.HIRATA: "An elementary processor architecture with simultaneous instruction issuing from multiple threads", PROC. 19TH ANNU. INT. SYMP. COMPUTER ARCH., 1992
  • GEORGE C. CLARK, ERROR-CORRECTION CODING FOR DIGITAL COMMUNICATIONS, 1981
  • VUCETIC; YUAN: "Turbo Codes: Principles and Applications", 2000, KLUWER ACADEMIC PUBLISHERS

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

DOCDB simple family (publication)

WO 02054601 A1 20020711; WO 02054601 A9 20030918; EP 1410513 A1 20040421; EP 1410513 A4 20050629; EP 2627008 A2 20130814; EP 2627008 A3 20130911; US 2002119803 A1 20020829; US 7230978 B2 20070612

DOCDB simple family (application)

US 0149478 W 20011228; EP 01985596 A 20011228; EP 13162380 A 20011228; US 4072701 A 20011228