EP 2705659 B1 20160727 - SHIFT REGISTER WITH TWO-PHASE NON-OVERLAPPING CLOCKS
Title (en)
SHIFT REGISTER WITH TWO-PHASE NON-OVERLAPPING CLOCKS
Title (de)
SCHIEBEREGISTER MIT ZWEIPHASIGEN NICHTÜBERLAPPENDEN TAKTEN
Title (fr)
REGISTRE À DÉCALAGE COMPORTANT DEUX HORLOGES À DEUX PHASES NON CHEVAUCHANTES
Publication
Application
Priority
- US 201161481968 P 20110503
- US 201213401517 A 20120221
- US 2012034792 W 20120424
Abstract (en)
[origin: WO2013015853A2] A method and apparatus for generating a first clock signal and a second clock signal with non-overlapping clock phases. In one example, the method may further include latching, by a plurality of master latches of a shift register, a plurality of values at a plurality of inputs of the master latches in response to a particular type of logical transition of the first clock signal. The method may also include latching, by a plurality of slave latches of the shift register, a plurality of output values of the plurality of master latches at a plurality of inputs of the slave latches in response particular type of logical transition of the second clock signal.
IPC 8 full level
G11C 19/00 (2006.01); H04N 5/335 (2006.01); H04N 5/355 (2011.01); H04N 5/3745 (2011.01)
CPC (source: EP US)
G11C 19/00 (2013.01 - US); H04N 25/00 (2023.01 - US); H04N 25/57 (2023.01 - EP US); H04N 25/772 (2023.01 - EP US)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
WO 2013015853 A2 20130131; WO 2013015853 A3 20130516; EP 2705659 A2 20140312; EP 2705659 B1 20160727; US 2014061442 A1 20140306; US 8890052 B2 20141118
DOCDB simple family (application)
US 2012034792 W 20120424; EP 12780898 A 20120424; US 201213401517 A 20120221