EP 3147777 A1 20170329 - RLS-DCD ADAPTATION HARDWARE ACCELERATOR FOR INTERFERENCE CANCELLATION IN FULL-DUPLEX WIRELESS SYSTEMS
Title (en)
RLS-DCD ADAPTATION HARDWARE ACCELERATOR FOR INTERFERENCE CANCELLATION IN FULL-DUPLEX WIRELESS SYSTEMS
Title (de)
RLS-DCD-ANPASSUNGS-HARDWAREBESCHLEUNIGER ZUR INTERFERENZUNTERDRÜCKUNG IN DRAHTLOSEN DUPLEXSYSTEMEN
Title (fr)
ACCÉLÉRATEUR MATÉRIEL D'ADAPTATION RLS-DCD POUR L'ANNULATION D'INTERFÉRENCES DANS DES SYSTÈMES SANS FIL EN DUPLEX INTÉGRAL
Publication
Application
Priority
US 201514861421 A 20150922
Abstract (en)
An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data. In addition, the hardware accelerator unit comprises a convergence detector unit configured to determine a convergence parameter; and a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter. The iteration signal communicates to the calculation unit and the adaptation core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the adaptation core unit.
IPC 8 full level
G06F 9/38 (2006.01)
CPC (source: CN EP US)
G06F 9/3877 (2013.01 - US); G06F 17/16 (2013.01 - EP US); H03H 21/0012 (2013.01 - EP US); H04L 5/0082 (2013.01 - CN); H04L 5/1446 (2013.01 - CN); H04L 25/03019 (2013.01 - CN); H03H 2021/0049 (2013.01 - EP US); H03H 2021/0094 (2013.01 - EP US); H03H 2218/06 (2013.01 - EP US); H04B 1/525 (2013.01 - EP US)
Citation (search report)
- [A] US 2007184782 A1 20070809 - SAHOTA GURKANWAL S [US], et al
- [XYI] LIU J ET AL: "FPGA Implementation of RLS Adaptive Filter Using Dichotomous Coordinate Descent Iterations", COMMUNICATIONS, 2009. ICC '09. IEEE INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 14 June 2009 (2009-06-14), pages 1 - 5, XP031506012, ISBN: 978-1-4244-3435-0
- [Y] ARABLOUEI REZA ET AL: "Recursive Total Least-Squares Algorithm Based on Inverse Power Method and Dichotomous Coordinate-Descent Iterations", IEEE TRANSACTIONS ON SIGNAL PROCESSING, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 63, no. 8, 1 April 2015 (2015-04-01), pages 1941 - 1949, XP011575666, ISSN: 1053-587X, [retrieved on 20150312], DOI: 10.1109/TSP.2015.2405492
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
EP 3147777 A1 20170329; CN 106549746 A 20170329; CN 106549746 B 20191220; US 2017085252 A1 20170323; US 9935615 B2 20180403
DOCDB simple family (application)
EP 16184520 A 20160817; CN 201610670816 A 20160815; US 201514861421 A 20150922