Global Patent Index - EP 3176669 A1

EP 3176669 A1 20170607 - CIRCUIT FOR GENERATING A REFERENCE VOLTAGE

Title (en)

CIRCUIT FOR GENERATING A REFERENCE VOLTAGE

Title (de)

SCHALTKREIS ZUR ERZEUGUNG EINER REFERENZSPANNUNG

Title (fr)

CIRCUIT DE GÉNÉRATION D'UNE TENSION DE RÉFÉRENCE

Publication

EP 3176669 A1 20170607 (FR)

Application

EP 16200987 A 20161128

Priority

FR 1561551 A 20151130

Abstract (en)

[origin: US2017153659A1] An FDSOI reference voltage generation circuit, including a CTAT current generation circuit; a PTAT-type voltage generation circuit including a first branch including first and second series-connected transistors, the front surface gates of the first and second transistors being connected to the conduction node of the second transistor opposite to the first transistor; a third diode-assembled transistor having a conduction node connected to an output node of the PTAT voltage generation circuit and having its other conduction node forming a reference voltage supply node; and a current mirror; wherein the first and second transistors are of LVT type and the third transistor is of RVT type.

Abstract (fr)

L'invention concerne un circuit FDSOI de génération d'une tension de référence (V REF ), comportant : un circuit (101) de génération d'un courant CTAT (I) ; un circuit (103) de génération d'une tension PTAT (V), comportant une première branche comportant des premier (N4) et deuxième (N5) transistors en série, les grilles de face avant des premier (N4) et deuxième (N5) transistors étant connectées au noeud de conduction du deuxième (N5) transistor opposé au premier transistor (N4) ; un troisième transistor (N8) monté en diode dont un noeud de conduction est connecté à un noeud de sortie du circuit de génération de la tension PTAT et dont l'autre noeud de conduction constitue un noeud de fourniture de la tension de référence (V REF ) ; et un miroir de courant (P2, P3, P5), dans lequel les premier (N4) et deuxième (N5) transistors sont de type LVT, et le troisième transistor (N8) est de type RVT.

IPC 8 full level

G05F 3/24 (2006.01)

CPC (source: EP US)

G05F 3/242 (2013.01 - EP US); G05F 3/267 (2013.01 - EP US)

Citation (applicant)

  • KEN UENO: "A 300 nW, 15 ppm/ C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, no. 7, July 2009 (2009-07-01), XP011263260, DOI: doi:10.1109/JSSC.2009.2021922
  • A. SAMIR: "173nA-7.5ppm/C-771mV-0.03mm2 CMOS Resistorless Voltage Reference", FAIBLE TENSION FAIBLE CONSOMMATION (FTFC, 2011
  • SONG QIN: "A 280NA , 87PPM/oC, HIGH PSRR FULL CMOS VOLTAGE REFERENCE AND ITS APPLICATION", IEEE
  • GIUSEPPE DE VITA: "A Sub-1-V, 10 ppm/ C, Nanopower Voltage Reference generator", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 42, no. 7, July 2007 (2007-07-01)
  • ANVESHA A: "A Sub-lV 32nA Process, Voltage and Temperature Invariant Voltage Reference Circuit", 26TH INTERNATIONAL CONFÉRENCE ON VLSI DESIGN, 2013
  • YUJI OSAKI: "1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 6, June 2013 (2013-06-01), XP011510721, DOI: doi:10.1109/JSSC.2013.2252523

Citation (search report)

  • [A] US 2012323508 A1 20121220 - VILAS BOAS ANDRE LUIS [BR], et al
  • [A] US 2012242398 A1 20120927 - OLMOS ALFREDO [US], et al
  • [A] US 2011121809 A1 20110526 - CAMACHO GALEANO EDGAR MAURICIO [BR], et al
  • [AD] UENO K ET AL: "A 300 nW, 15 ppm/C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 44, no. 7, 1 July 2009 (2009-07-01), pages 2047 - 2054, XP011263260, ISSN: 0018-9200, DOI: 10.1109/JSSC.2009.2021922
  • [A] JÃ CR RÃ'ME MAZURIER ET AL: "On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 58, no. 8, 1 August 2011 (2011-08-01), pages 2326 - 2336, XP011336343, ISSN: 0018-9383, DOI: 10.1109/TED.2011.2157162
  • [A] JANI MAKIPAA ET AL: "FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?", CIRCUITS AND SYSTEMS (ISCAS), 2013 IEEE INTERNATIONAL SYMPOSIUM ON, IEEE, 19 May 2013 (2013-05-19), pages 554 - 557, XP032445978, ISBN: 978-1-4673-5760-9, DOI: 10.1109/ISCAS.2013.6571903
  • [A] ARNAUD F: "Enhanced low voltage digital & analog mixed-signal with 28nm FDSOI technology", 2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), IEEE, 5 October 2015 (2015-10-05), pages 1 - 4, XP032815123, DOI: 10.1109/S3S.2015.7333503

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

DOCDB simple family (publication)

EP 3176669 A1 20170607; EP 3176669 B1 20190109; US 10037047 B2 20180731; US 2017153659 A1 20170601

DOCDB simple family (application)

EP 16200987 A 20161128; US 201615365039 A 20161130