EP 3176978 B1 20180620 - CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PODL WIRE FAULTS
Title (en)
CIRCUIT ARCHITECTURES FOR PROTECTING AGAINST PODL WIRE FAULTS
Title (de)
SCHALTUNGSARCHITEKTUREN ZUM SCHUTZ GEGEN PODL-DRAHTFEHLER
Title (fr)
ARCHITECTURES DE CIRCUIT POUR LA PROTECTION CONTRE LES DÉFAILLANCES DE CÂBLE PODL
Publication
Application
Priority
US 201514956308 A 20151201
Abstract (en)
[origin: EP3176978A1] In one embodiment, a PoDL system includes a PSE that uses high side (30) and low side (32) circuit breakers that uncouple the PSE voltage source (20) from the wire pair (18) in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires (18). The breakers (30,32) perform an automatic retry operation in the event the fault has been removed. The voltages on the wires (18) in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.
IPC 8 full level
H04L 12/10 (2006.01); G06F 1/26 (2006.01); H04L 12/24 (2006.01); H04L 12/40 (2006.01)
CPC (source: EP KR)
H04L 12/10 (2013.01 - EP KR); H04L 12/40045 (2013.01 - EP); H04L 25/0266 (2013.01 - KR); H04L 43/08 (2013.01 - EP KR); H04L 43/16 (2013.01 - EP)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
EP 3176978 A1 20170607; EP 3176978 B1 20180620; KR 102002672 B1 20190722; KR 20170064484 A 20170609
DOCDB simple family (application)
EP 16002547 A 20161130; KR 20160161370 A 20161130